MCP19116-ESLASHMJ datasheet(115/246 Pages) MICROCHIP

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 2015-2016 Microchip Technology Inc.

DS20005479B-page 115

MCP19116/7

16.0 POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP instruction.

Upon entering Sleep mode, the following conditions

occur:

WDT is cleared but keeps running, if enabled for

operation during Sleep.

PD bit in the STATUS register is cleared.

TO bit in the STATUS register is set.

CPU clock is disabled.

The ADC is inoperable due to the absence of the

4V LDO power (AVDD) when the ADC reference

is set to AVDD.

I/O ports maintain the status they had before

SLEEP was executed (driving high, low or

high-impedance).

Resets other than WDT and BOR are not

affected by Sleep mode.

Analog Circuit power (AVDD) is removed during

Sleep mode.

To minimize sleep current the ADC Reference

must be set to AVDD (default).

Refer to individual chapters for more details on

peripheral operation during Sleep.

To minimize current consumption, the following

conditions should be considered:

• I/O pins should not be floating (1)

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using Timer1 oscillator

• ADC Reference should be set to the default con-

dition (AVDD).

•VDR will draw a small amount of current from VDD

if VDD is connected to VDR externally. To achieve

minimum Sleep current, disconnect VDR from VDD

during Sleep.

Note 1: It is recommended that the I/O pins that are

high-impedance inputs be pulled to VDD or

GND externally to avoid switching currents

caused by floating inputs.

The SLEEP instruction removes power from the analog

circuitry. AVDD is shut down to minimize current draw in

Sleep mode and to maintain a shutdown current of

50 µA typical. The 5V LDO (VDD) voltage drops to 2.9V

minimum in Sleep mode. External current draw from

the 5V LDO (VDD) should be limited to less than 1 mA.

Loads drawing more than 1 mA externally during Sleep

mode risk loading down the VDD voltage and tripping

POR. A POR event during Sleep mode will wake the

device from Sleep. The enable state of the analog

circuitry does not change with the execution of the

SLEEP instruction.

16.1

Wake-Up from Sleep

The device can wake up from Sleep through one of the

following events:

External Reset input on MCLR pin, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information)

The first two events will cause a device reset. The last

three events are considered a continuation of program

execution. To determine whether a device reset or

wake-up event occurred, refer to Section 14.7

“Determining the Cause of a Reset”.

The following peripheral interrupts can wake the device

from Sleep:

Interrupt-on-change

External Interrupt from INT pin

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEP instruction and will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NO OPERATION (NOP) after the SLEEP

instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

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