TMS570LS3134 datasheet(46/167 Pages) TI1

46 / 167 page

VCCIO

VIH

VIL

Input

tpw

VIL

TMS570LS3134, TMS570LS2134, TMS570LS2124

SPNS165B – APRIL 2012 – REVISED MAY 2015

www.ti.com

5.11 Input Timings

Figure 5-2. TTL-Level Inputs

Table 5-6. Timing Requirements for Inputs(1)

MIN

MAX

UNIT

tpw

Input minimum pulse width

tc(VCLK) + 10

(2)

(1)

tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)

(2)

The timing shown in Figure 5-2 is only valid for pins used in GPIO mode.

5.12 Output Timings

Table 5-7. Switching Characteristics for Output Timings Versus Load Capacitance (CL)

PARAMETER

MIN

MAX

UNIT

CL = 15 pF

2.5

CL = 50 pF

Rise time, tr

CL = 100 pF

7.2

CL = 150 pF

12.5

8 mA low EMI pins

(see Table 5-4)

CL = 15 pF

2.5

CL = 50 pF

Fall time, tf

CL = 100 pF

7.2

CL = 150 pF

12.5

CL = 15 pF

5.6

CL = 50 pF

10.4

Rise time, tr

CL = 100 pF

16.8

CL = 150 pF

23.2

4 mA low EMI pins

(see Table 5-4)

CL = 15 pF

5.6

CL= 50 pF

10.4

Fall time, tf

CL = 100 pF

16.8

CL = 150 pF

23.2

CL = 15 pF

CL = 50 pF

Rise time, tr

CL = 100 pF

CL = 150 pF

2 mA-z low EMI pins

(see Table 5-4)

CL = 15 pF

CL = 50 pF

Fall time, tf

CL = 100 pF

CL = 150 pF

Specifications

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