EMC1184 datasheet(29/48 Pages) MICROCHIP

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Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications

Datasheet

SMSC EMC1184

Revision 1.0 (07-11-13)

DATASHEET

As shown in Table 6.2, all temperatures are stored as an 11-bit value with the high byte representing

the integer value and the low byte representing the fractional value left justified to occupy the MSBits.

6.3

Status Register 02h

The Status Register reports general error conditions. To identify specific channels, refer to

Section 6.10, Section 6.15, Section 6.16, and Section 6.17. The individual Status Register bits are

cleared when the appropriate High Limit, Low Limit, or Therm Limit register has been read or cleared.

Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either

the ALERT / THERM2 or THERM pin to be asserted.

Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit.

See the High Limit Status Register for specific channel information (Section 6.15). When set, this bit

will assert the ALERT / THERM2 pin.

Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low

limit. See the Low Limit Status Register for specific channel information (Section 6.16). When set, this

bit will assert the ALERT / THERM2 pin.

Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode

channels. See the External Diode Fault Register for specific channel information (Section 6.10). When

set, this bit will assert the ALERT / THERM2 pin.

Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed

Therm Limit. See the Therm Limit Status Register for specific channel information (Section 6.17).

When set, this bit will assert the THERM pin.

6.4

Configuration Register 03h / 09h

The Configuration Register controls the basic operation of the device. This register is fully accessible

at either address.

Bit 7 - MASK_ALL - Masks the ALERT / THERM2 pin from asserting.



‘0’ - (default) - The ALERT / THERM2 pin is not masked. If any of the appropriate status bits are

set the ALERT / THERM2 pin will be asserted.



‘1’ - The ALERT/ THERM2 pin is masked. It will not be asserted for any interrupt condition unless

it is configured in comparator mode. The Status Registers will be updated normally.

Table 6.3 Status Register

ADDR

R/W

DEFAULT

02h

Status

BUSY

HIGH

LOW

FAULT

THERM

00h

Table 6.4 Configuration Register

ADDR

R/W

DEFAULT

03h

R/W

Configuration

MASK_

ALL

-ALERT/

THERM2

RECD1

RECD2

RANGE

DAVG_

DIS

APDD

80h

09h

EMC1184 Datasheet(PDF) 29 Page - Microchip Technology

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