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EMC1184 Datasheet(PDF) 40 Page - Microchip Technology |
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EMC1184 Datasheet(HTML) 40 Page - Microchip Technology |
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40 / 48 page ![]() Quad Channel 1°C Temperature Sensor with Beta Compensation and 1.8V SMBus Communications Datasheet Revision 1.0 (07-11-13) 40 SMSC EMC1184 DATASHEET 6.15 High Limit Status Register 35h The High Limit Status Register contains the status bits that are set when a temperature channel high limit is exceeded. If any of these bits are set, the HIGH status bit in the Status Register is set. Reading from the High Limit Status Register will clear all bits if. Reading from the register will also clear the HIGH status bit in the Status Register. The ALERT / THERM2 pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set. The status bits will remain set until read unless the ALERT / THERM2 pin is configured as a comparator output (see Section 5.5.2). Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel exceeds its programmed high limit. Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high limit. Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit. Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit. 6.16 Low Limit Status Register 36h The Low Limit Status Register contains the status bits that are set when a temperature channel drops below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear the LOW status bit in the Status Register. The ALERT / THERM2 pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set. The status bits will remain set until read unless the ALERT / THERM2 pin is configured as a comparator output (see Section 5.5.2). Bit 3 - This bit is set when the External Diode 3 channel drops below its programmed low limit. Bit 2 - E2LOW - This bit is set when the External Diode 2 channel drops below its programmed low limit. Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low limit. Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit. Table 6.20 High Limit Status Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 35h R-C High Limit Status - - - - E3HIGH E2HIGH EHIGH IHIGH 00h Table 6.21 Low Limit Status Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 36h R-C Low Limit Status - - - - E3LOW E2LOW ELOW ILOW 00h |
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