STM32L081CB datasheet(18/110 Pages) STMICROELECTRONICS

18 / 110 page

Functional overview

STM32L081xx

18/110

DocID027513 Rev 4

3.3

ARM® Cortex®-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a

broad range of embedded applications. It offers significant benefits to developers, including:



a simple architecture that is easy to learn and program



ultra-low power, energy-efficient operation



excellent code density



deterministic, high-performance interrupt handling



upward compatibility with Cortex-M processor family



platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor

core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional

energy efficiency through a small but powerful instruction set and extensively optimized

design, providing high-end processing hardware including a single-cycle multiplier.

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-

bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded ARM core, the STM32L081xx are compatible with all ARM tools and

software.

RTC

TIM21

Timer triggered by Auto

wake-up

LPTIM

Timer triggered by RTC

event

All clock

source

TIMx

Clock source used as

input channel for RC

measurement and

trimming

GPIO

TIMx

Timer input channel and

trigger

LPTIM

Timer input channel and

trigger

ADC

Conversion trigger

Table 5. STM32L0xx peripherals interconnect matrix (continued)

Interconnect

source

Interconnect

destination

Interconnect action

Run Sleep

Low-

power

run

Low-

power

sleep

Stop

STM32L081CB Datasheet(PDF) 18 Page - STMicroelectronics

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