STM32L081CB datasheet(20/110 Pages) STMICROELECTRONICS

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Functional overview

STM32L081xx

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DocID027513 Rev 4

internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when

VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external

reset circuit.

Note:

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-

up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive

at power-up.

The devices feature an embedded programmable voltage detector (PVD) that monitors the

VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different

levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An

interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when

VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate

a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.4.3

Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.



MR is used in Run mode (nominal regulation)



LPR is used in the Low-power run, Low-power sleep and Stop modes



Power down is used in Standby mode. The regulator output is high impedance, the

kernel circuitry is powered down, inducing zero consumption but the contents of the

registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,

LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

3.5

Clock management

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:



Clock prescaler

To get the best trade-off between speed and current consumption, the clock frequency

to the CPU and peripherals can be adjusted by a programmable prescaler.



Safe clock switching

Clock sources can be changed safely on the fly in Run mode through a configuration



Clock management

To reduce power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory.



System clock source

Three different clock sources can be used to drive the master clock SYSCLK:

–

1-25 MHz high-speed external crystal (HSE), that can supply a PLL

–

16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can

supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able

to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1

MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),

the MSI frequency can be trimmed by software down to a ±0.5% accuracy.



Auxiliary clock source

Two ultra-low-power clock sources that can be used to drive the real-time clock:

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