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STM8S903K3 Datasheet(PDF) 55 Page - STMicroelectronics |
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STM8S903K3 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 121 page ![]() DocID15590 Rev 10 55/121 STM8S903K3 STM8S903F3 Electrical characteristics 88 Figure 10. fCPUmax versus VDD Table 22. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2 - µs/V VDD fall time rate(1) 1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed. -2 - tTEMP Reset release delay VDD rising - - 1.7 ms VIT+ Power-on reset threshold - 2.6 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8 VHYS(BOR) Brown-out reset hysteresis -- 70 - mV |
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