| Electronic Components Datasheet Search |
|
STM8S903K3 Datasheet(PDF) 83 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM8S903K3 Datasheet(HTML) 83 Page - STMicroelectronics |
|
83 / 121 page ![]() DocID15590 Rev 10 83/121 STM8S903K3 STM8S903F3 Electrical characteristics 88 10.3.10 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 47. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit fADC ADC clock frequency VDD= 2.95 to 5.5 V 1 - 4 MHz VDD= 4.5 to 5.5 V 1 - 6 VAIN Conversion voltage range(1) 1. During the sample time, the sampling capacitance, CAIN (3 pF max), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. - VSS - VDD V CADC Internal sample and hold capacitor -- 3 - pF tS(1) Minimum sampling time fADC = 4 MHz - 0.75 - µs fADC = 6 MHz - 0.5 - tSTAB Wakeup time from standby - - 7 - µs tCONV Minimum total conversion time (including sampling time, 10- bit resolution) fADC = 4 MHz 3.5 µs fADC = 6 MHz 2.33 µs -14 1/fADC |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |