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AS4SD16M16 Datasheet(PDF) 18 Page - Micross Components

Part # AS4SD16M16
Description  LVTTL- compatible inputs and outputs
PDF  52 Pages
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Manufacturer  MICROSS [Micross Components]
Direct Link  http://www.micross.com
Logo MICROSS - Micross Components

AS4SD16M16 Datasheet(HTML) 18 Page - Micross Components

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SDRAM
AS4SD16M16
AS4SD16M16
Rev. 2.6 04/13/15
Micross Components reserves the right to change products or specifications without notice.
18
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncate a
WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data writ-
ten (provided that DQM is LOW at that time) will be the input
data applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (see Figure 20) is used to
deactivate the open row in a particular bank or the open row
in all banks. The bank(s) will be available for a subsequent
row access some specified time (t
RP) after the PRECHARGE
command is issued. Input A10 determines whether one or all
banks are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank. When
all banks are to be precharged, inputs BA0, BA1 are treated as
“Don’t Care”. Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident
with a NOP or COMMAND INHIBIT when no accesses are
in progress. If power-down occurs when all banks are idle,
this mode is referred to as precharge power-down; if power-
down occurs when there is a row active in any bank, this mode
is referred to as active power-down. Entering power-down
deactivates the input and output buffers, excluding CKE, for
maximum power saving while in standby. The device may
not remain in the power-down state longer then the refresh
period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering a NOP or
COMMAND INHIBIT and CKE HIGH at the desired clock
edge (meeting tCKS). See Figure 21.
FIGURE 20: PRECHARGE Command
FIGURE 19: Terminating a WRITE
Burst
FIGURE 21: Power-Down



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