AS4SD16M16 datasheet(30/52 Pages) MICROSS

30 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

NOTES:

1. All voltages referenced to V

SS.

2. This parameter is sampled. V

DD, VDDQ = +3.3V; f = 1 MHz,

A = 25°C; pin under test biased at 1.4V.

3. I

DD is dependent on output loading and cycle rates. Speci-

fied values are obtained with minimum cycle time and the

outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle

time at which proper operation over the full temperature range

is ensured:

(0°C < T

A < +125°C for XT), (-40°C < TA <

+85°C for IT), and (-45°C < T

A < +105°C for ET).

6.An initial pause of 100µs is required after power-up, followed

by two AUTO REFRESH commands, before proper device

operation is ensured. (V

DD and VDDQ must be powered up si-

multaneously. V

SS and VSSQ must be at the same potential.) The

twoAUTO REFRESH command wake-ups should be repeated

any time the tREF refresh requirement is

exceeded.

7. AC characteristics assume t

T = 1ns.

8. In addition to meeting the transition rate specification, the

clock and CKE must transit between V

IH and VIL (or between

IL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. t

HZ defines the time at which the output achieves the open

circuit condition; it is not a reference to V

OH or VOL. The last

valid data element will meet t

OH before going High-Z.

11. AC operating and I

DD test conditions have VIL = 0V and

IH = 3.0V using a measurement reference level of 1.5V. If

the input transition time is longer than 1ns, then the timing is

measured from V

IL (MAX) and

IH (MIN) and no longer

from the 1.5V mid-point.

12. Other input signals are allowed to transition no more than

once every two clocks and are otherwise at valid V

IH or VIL

levels.

13. I

DD specifications are tested after the device is properly

initialized.

14. Timing actually specified by t

CKS; clock(s) specified as a

reference only at minimum cycle rate.

15. Timing actually specified by t

WR plus tRP; clock(s) specified

as a reference only at minimum cycle rate.

16. Timing actually specified by t

WR.

17. Required clocks are specified by JEDEC functionality and

are not dependent on any timing parameter.

18. The I

DD current will increase or decrease proportionally

according to the amount of frequency alteration for the test

condition.

19. Address transitions average one transition every two

clocks.

20. CLK must be toggled a minimum of two times during this

period.

21. Based on t

CK = 7.5ns for -75.

22. V

IH overshoot: VIL (MAX) = VDDQ = 2V for a pulse width

< 3ns, and the pulse width cannot be greater than one third of

the cycle rate. V

IL undershoot: VIL (MIN) = -2V for a pulse

width < 3ns.

23. The clock frequency must remain constant (stable clock is

defined as a signal cycling within timing constraints specified

for the clock pin) during access or precharge states (READ,

WRITE, including t

WR, and PRECHARGE commands). CKE

may be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget

RP) begins 7.5ns after the first clock delay, after the last WRITE

is executed. May not exceed limit set for precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clock.

27. for -75 at CL = 3 with no load is 4.6ns and is guaranteed

by design.

28. Parameter guaranteed by design.

29. PC100 specifies a maximum of 4pF.

30. PC100 specifies a maximum of 5pF.

31. PC100 specifies a maximum of 6.5pF.

32. CL = 3 and tCK = 7.5ns.

33. CKE is HIGH during refresh command period t

RFC (MIN)

else CKE is LOW. The I

DD6 limit is actually a nominal value

and does not result in a fail value.

34. 64ms refresh for IT, ET temperature options, 24ms refresh

for XT temperature option.

35. Self refresh mode available for IT and ET only.

SDRAM

AS4SD16M16

Rev. 1.7 3/2/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

Austin Semiconductor, Inc.

NOTES:

1. All voltages referenced to V

SS.

2. This parameter is sampled. V

DD, VDDQ = +3.3V; f = 1 MHz, TA

= 25°C; pin under test biased at 1.4V.

3. I

DD is dependent on output loading and cycle rates. Speci-

fied values are obtained with minimum cycle time and the out-

puts open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle

time at which proper operation over the full temperature range

is ensured:

(0°C < T

A < +125°C for XT), (-40°C < TA < +85°C

for IT), and (-45°C < T

A < +105°C for IT+).

6. An initial pause of 100µs is required after power-up, followed

by two AUTO REFRESH commands, before proper device op-

eration is ensured. (V

DD and VDDQ must be powered up simul-

taneously. V

SS and VSSQ must be at the same potential.) The

two AUTO REFRESH command wake-ups should be repeated

any time the tREF refresh requirement is

exceeded.

7. AC characteristics assume t

T = 1ns.

8. In addition to meeting the transition rate specification, the

clock and CKE must transit between V

IH and VIL (or between VIL

and V

IH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. t

HZ defines the time at which the output achieves the open

circuit condition; it is not a reference to V

OH or VOL. The last

valid data element will meet t

OH before going High-Z.

11. AC operating and I

DD test conditions have VIL = 0V and VIH

= 3.0V using a measurement reference level of 1.5V. If the input

transition time is longer than 1ns, then the timing is measured

from V

IL (MAX) and

IH (MIN) and no longer from the 1.5V

mid-point.

12. Other input signals are allowed to transition no more than

once every two clocks and are otherwise at valid V

IH or VIL

levels.

13. I

DD specifications are tested after the device is properly ini-

tialized.

14. Timing actually specified by t

CKS; clock(s) specified as a

reference only at minimum cycle rate.

15. Timing actually specified by t

WR plus tRP; clock(s) specified

as a reference only at minimum cycle rate.

16. Timing actually specified by t

WR.

17. Required clocks are specified by JEDEC functionality and

are not dependent on any timing parameter.

18. The I

DD current will increase or decrease proportionally ac-

cording to the amount of frequency alteration for the test con-

dition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this

period.

21. Based on t

CK = 7.5ns for -75.

22. V

IH overshoot: VIL (MAX) = VDDQ = 2V for a pulse width <

3ns, and the pulse width cannot be greater than one third of the

cycle rate. V

IL undershoot: VIL (MIN) = -2V for a pulse width <

3ns.

23. The clock frequency must remain constant (stable clock is

defined as a signal cycling within timing constraints specified

for the clock pin) during access or precharge states (READ,

WRITE, including t

WR, and PRECHARGE commands). CKE

may be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget

RP) begins 7.5ns after the first clock delay, after the last WRITE

is executed. May not exceed limit set for precharge mode.

25. Precharge mode only.

26. JEDEC and PC100 specify three clock.

27. for -75 at CL = 3 with no load is 4.6ns and is guaranteed by

design.

28. Parameter guaranteed by design.

29. PC100 specifies a maximum of 4pF.

30. PC100 specifies a maximum of 5pF.

31. PC100 specifies a maximum of 6.5pF.

32. CL = 3 and tCK = 7.5ns.

33. CKE is HIGH during refresh command period t

RFC (MIN) else

CKE is LOW. The I

DD6 limit is actually a nominal value and

does not result in a fail value.

34. 64ms refresh for IT, IT+ temperature options, 24ms refresh

for XT temperature option.

35. Self refresh mode available for IT and IT+ only.

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