AS4SD16M16 datasheet(26/52 Pages) MICROSS

26 / 52 page

SDRAM

AS4SD16M16

Rev. 2.6 04/13/15

Micross Components reserves the right to change products or specifications without notice.

NOTES (continued):

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state

only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: bank n will initiate the auto precharge command when its burst has been interrupted

by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE com-

mand to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid

WRITE to bank n will be data-in registered one clock prior to the READ on bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will inter-

rupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered

(Figure 25).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus

contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n

will begin after t

WR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be

data-in registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t

WR is met, where tWR begins

when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE

to bank m (Figure 27).

AS4SD16M16 Datasheet(PDF) 26 Page - Micross Components