CPU Supervisor with Nonvolatile Memory and

Programmable I/O

8

_____________________________________________________________________

The following terminology is commonly used to

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses, start, and stop conditions.

Slave Devices: Slave devices send and receive data

at the master’s request.

Bus Idle or Not Busy: Time between stop and start

conditions when both SDA and SCL are inactive and in

their logic-high states. When the bus is idle it often initi-

ates a low-power mode for slave devices.

Start Condition: A start condition is generated by the

master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a start condition. See the timing dia-

gram for applicable timing.

Stop Condition: A stop condition is generated by the

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high gener-

applicable timing.

Repeated Start Condition: The master can use a

repeated start condition at the end of one data transfer

to indicate that it will immediately initiate a new data

transfer following the current one. Repeated starts are

commonly used during read operations to identify a

specific memory address to begin a data transfer. A

repeated start condition is issued identically to a nor-

applicable timing.

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL (see

Data is shifted into the device during the rising edge of

the SCL.

Bit Read: At the end a write operation, the master must

release the SDA bus line for the proper amount of setup

REGISTER BIT NAMES

REGISTER

NAME

REGISTER

LOCATION

(HEX)

Bit 7

Bit 6

Bit5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FACTORY OR

POWER-ON

DEFAULT

(BIN)

User

EEPROM

00-3F

EE

EE

EE

EE

EE

EE

EE

EE

00000000

Reserved

40-EF

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

n/a

Pullup

Enable

F0

SEE

SEE

SEE

SEE

I/O3

pullup

I/O2

pullup

I/O1

pullup

I/O0

pullup

00000000

RST Delay

F1

SEE

SEE

SEE

SEE

SEE

SEE

TD1

TD0

00000011

User SEE

F2

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

00000000

User SEE

F3

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

00000000

I/O3

Control

F4

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O3

00000001

I/O2

Control

F5

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O2

00000001

I/O1

Control

F6

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O1

00000001

I/O0

Control

F7

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O0

00000001

I/O Status

F8

0

0

00

I/O3

Status

I/O2

Status

I/O1

Status

I/O0

Status

n/a

Config

F9

ready

trip point

reset

status

SEE

SWRST

00

0

XXX00000

User SRAM

FA-FF

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

SRAM

00000000

Figure 4. Register Bit Names