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DS4510U-5/T Datasheet(PDF) 10 Page - Maxim Integrated Products |
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DS4510U-5/T Datasheet(HTML) 10 Page - Maxim Integrated Products |
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10 / 12 page ![]() CPU Supervisor with Nonvolatile Memory and Programmable I/O 10 ____________________________________________________________________ address pin allows for the DS4510 to respond to one of two slave addresses (1010000X, or 1010001X). If the R/ W bit is zero, the master writes data to the slave. If the R/ W is one, the master reads data from the slave. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte trans- mitted during a write operation following the slave address byte (R/ W = 0). I2C Communications Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address (R/ W= 0), write the memory address, write the byte of data and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing a Multiple Bytes to a Slave: To write multiple bytes to a slave the master generates a start condition, writes the slave address (R/ W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. The DS4510 can write 1 to 8 bytes (one page or row) with a single write transaction. This is internally con- trolled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory table, see Figure 3). Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the pre- sent row. Example: A 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three “consecutive” addresses. The result would be address- es 06h and 07h would contain 11h and 22h, respective- ly, and the third data byte, 33h, would be written to address 00h. To prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. The master may then generate a new start con- tSP tHD:STA tSU:STA tSU:DAT tHD:DAT tHIGH tF tR tHD:STA START STOP NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN) tLOW tBUF SDA SCL REPEATED START tSU:STO Figure 5. I2C Timing Diagram 7-BIT SLAVE ADDRESS MOST SIGNIFICANT BIT 10 1 000 A0 R/W A0 PIN VALUE DETERMINES READ OR WRITE Figure 6. DS4510’s Slave Address and the R/ W Bit |
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