A3G4250D datasheet(31/44 Pages) STMICROELECTRONICS

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A3G4250D

Doc 022768 Rev 3

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The device contains a set of registers which are used to control its behavior and to retrieve

rate data. The register addresses, made up of 7 bits, are used to identify them and to write

the data through the serial interface.

7.1

WHO_AM_I (0Fh)

Device identification register.

7.2

CTRL_REG1 (20h)

DR<1:0> is used to set ODR selection. BW <1:0> is used to set Bandwidth selection.

In the following table (Table 22) all frequencies resulting in a combination of DR / BW bits

are reported.

Table 19.

WHO_AM_I register

10100

Table 20.

CTRL_REG1 register

DR1

DR0

BW1

BW0

Zen

Yen

Xen

Table 21.

CTRL_REG1 description

DR1-DR0

Output data rate selection. Refer to Table 22

BW1-BW0

Bandwidth selection. Refer to Table 22

Power-down mode enable. Default value: 0

(0: power-down mode, 1: normal mode or sleep mode)

Zen

Z-axis enable. Default value: 1

(0: Z-axis disabled; 1: Z-axis enabled)

Yen

Y-axis enable. Default value: 1

(0: Y-axis disabled; 1: Y-axis enabled)

Xen

X-axis enable. Default value: 1

(0: X-axis disabled; 1: X-axis enabled)

Table 22.

DR and BW configuration setting

DR <1:0>

BW <1:0>

ODR [Hz]

Cut-off

100

12.5

100

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