A3G4250D datasheet(35/44 Pages) STMICROELECTRONICS

35 / 44 page

A3G4250D

Doc 022768 Rev 3

35/44

Figure 18.

INT1_Sel and Out_Sel configuration block diagram

Table 35.

Out_Sel configuration settings

Hpen

OUT_SEL1

OUT_SEL0

Description

Data in DataReg and FIFO are non-high-

pass-filtered

Data in DataReg and FIFO are high-pass-

filtered

Data in DataReg and FIFO are low-pass-

filtered by LPF2

Data in DataReg and FIFO are high-pass and

low-pass-filtered by LPF2

Table 36.

INT_SEL configuration settings

Hpen

INT_SEL1

INT_SEL2

Description

Non-high-pass-filtered data are used for

interrupt generation

High-pass-filtered data are used for interrupt

generation

Low-pass-filtered data are used for interrupt

generation

High-pass and low-pass-filtered data are

used for interrupt generation

ADC

LPF1

HPF

HPen

LPF2

Out_Sel <1:0>

DataReg

FIFO

32x16x3

Interrupt

generator

INT1_Sel <1:0>

AM07949V2

A3G4250D Datasheet(PDF) 35 Page - STMicroelectronics

A3G4250D Datasheet(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL