SPC564A70L7 datasheet(16/133 Pages) STMICROELECTRONICS

16 / 133 page

Introduction

SPC564A70B4, SPC564A70L7

16/133

Doc ID 18078 Rev 4

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Synthesizeable, MuxD scan design

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ABIST/MBIST for arrays

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Built-in Parallel Signature Unit

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Calibration support allowing an external tool to modify address mapping

1.5.2

Crossbar switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between four

master ports and four slave ports. The crossbar supports a 32-bit address bus width and a

64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any

slave port but each master must access a different slave. If a slave port is simultaneously

requested by more than one master port, arbitration logic selects the higher priority master

and grants it ownership of the slave port. All other masters requesting that slave port are

stalled until the higher priority master completes its transactions. Requesting masters are

treated with equal priority and are granted access to a slave port in round-robin fashion,

based upon the ID of the last master to be granted access. The crossbar provides the

following features:

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4 master ports

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CPU instruction bus

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CPU data bus

–eDMA

–FlexRay

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4 slave ports

–Flash

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Calibration bus interface

–SRAM

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Peripheral bridge

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32-bit internal address, 64-bit internal data paths

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module

capable of performing complex data movements via 64 programmable channels, with

minimal intervention from the host processor. The hardware micro-architecture includes a

DMA engine which performs source and destination address calculations, and the actual

data movement operations, along with an SRAM-based memory containing the transfer

control descriptors (TCD) for the channels. This implementation minimizes overall block

size. The eDMA module provides the following features:

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All data movement via dual-address transfers: read from source, write to destination

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Programmable source and destination addresses, transfer size, plus support for

enhanced addressing modes

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Transfer control descriptor organized to support two-deep, nested transfer operations

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An inner data transfer loop defined by a “minor” byte transfer count

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An outer data transfer loop defined by a “major” iteration count

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