SPC564A70L7 datasheet(18/133 Pages) STMICROELECTRONICS

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Introduction

SPC564A70B4, SPC564A70L7

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Doc ID 18078 Rev 4

system bus transactions and evaluates the appropriateness of each transfer. Memory

references with sufficient access control rights are allowed to complete; references that are

not mapped to any region descriptor or have insufficient rights are terminated with a

protection error response.

The MPU has these major features:

●

Support for 16 memory region descriptors, each 128 bits in size

–

Specification of start and end addresses provide granularity for region sizes from

32 bytes to 4 GB

–

MPU is invalid at reset, thus no access restrictions are enforced

–

2 types of access control definitions: processor core bus master supports the

traditional {read, write, execute} permissions with independent definitions for

supervisor and user mode accesses; the remaining non-core bus masters (eDMA,

FlexRay) support {read, write} attributes

–

Automatic hardware maintenance of the region descriptor valid bit removes issues

associated with maintaining a coherent image of the descriptor

–

Alternate memory view of the access control word for each descriptor provides an

efficient mechanism to dynamically alter the access rights of a descriptor only

–

For overlapping region descriptors, priority is given to permission granting over

access denying as this approach provides more flexibility to system software

●

Support for two XBAR slave port connections (SRAM and PBRIDGE)

–

For each connected XBAR slave port (SRAM and PBRIDGE), MPU hardware

monitors every port access using the preprogrammed memory region descriptors

–

An access protection error is detected if a memory reference does not hit in any

memory region or the reference is flagged as illegal in all memory regions where it

does hit. In the event of an access error, the XBAR reference is terminated with an

error response and the MPU inhibits the bus cycle being sent to the targeted slave

device

–

64-bit error registers, one for each XBAR slave port, capture the last faulting

address, attributes, and detail information

1.5.6

Frequency-modulated phase-locked loop (FMPLL)

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz

crystal oscillator or external clock generator. Further, the FMPLL supports programmable

frequency modulation of the system clock. The PLL multiplication factor, output clock divider

ratio are all software configurable. The PLL has the following major features:

●

Input clock frequency from 4 MHz to 40 MHz

●

Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

●

3 modes of operation

–

Bypass mode with PLL off

–

Bypass mode with PLL running (default mode out of reset)

–

PLL normal mode

●

Each of the 3 modes may be run with a crystal oscillator or an external clock reference

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