SPC564A70L7 datasheet(20/133 Pages) STMICROELECTRONICS

20 / 133 page

Introduction

SPC564A70B4, SPC564A70L7

20/133

Doc ID 18078 Rev 4

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Internal multiplexing

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Allows serial and parallel chaining of DSPIs

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Allows flexible selection of eQADC trigger inputs

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Allows selection of interrupt requests between external pins and DSPI

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From a set of eTPU output channels, allows selection of source signals for

decimation filter integrators

1.5.8

Flash memory

The SPC564A70 provides 2 MB of programmable, non-volatile, flash memory. The non-

volatile memory (NVM) can be used to store instructions or data, or both. The flash module

includes a Fetch Accelerator that optimizes the performance of the flash array to match the

CPU architecture. The flash module interfaces the system bus to a dedicated flash memory

array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-

bit data bus width at the system bus port, and 128-bit read data interfaces to flash memory.

The module contains a prefetch controller which prefetches sequential lines of data from the

flash array into the buffers. Prefetch buffer hits allow no-wait responses.

The flash memory provides the following features:

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Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte,

halfword, word and doubleword reads are supported. Only aligned word and

doubleword writes are supported.

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Fetch Accelerator

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Architected to optimize the performance of the flash

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Configurable read buffering and line prefetch support

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4-entry 128-bit wide line read buffer

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Prefetch controller

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Hardware and software configurable read and write access protections on a per-master

basis

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Interface to the flash array controller pipelined with a depth of one, allowing overlapped

accesses to proceed in parallel for pipelined flash array designs

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Configurable access timing usable in a wide range of system frequencies

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Multiple-mapping support and mapping-based block access timing (0–31 additional

cycles) usable for emulation of other memory types

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Software programmable block program/erase restriction control

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Erase of selected block(s)

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Read page size of 128 bits (4 words)

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ECC with single-bit correction, double-bit detection

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Program page size of 128 bits (4 words) to accelerate programming

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ECC single-bit error corrections are visible to software

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Minimum program size is 2 consecutive 32-bit words, aligned on a 0-modulo-8 byte

address, due to ECC

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Embedded hardware program and erase algorithm

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Erase suspend, program suspend and erase-suspended program

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Shadow information stored in non-volatile shadow block

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Independent program/erase of the shadow block

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