SPC564A70L7 datasheet(21/133 Pages) STMICROELECTRONICS

21 / 133 page

SPC564A70B4, SPC564A70L7

Introduction

Doc ID 18078 Rev 4

21/133

1.5.9

Static random access memory (SRAM)

The SRAM provides 128 KB of general purpose system SRAM. The first 32 KB block of the

SRAM is powered by its own power supply pin only during standby operation.

The SRAM controller includes these features:

●

128 KB data RAM implemented as eight 16 KB (2048

× 78 bits) blocks

●

Each 16 KB block has 2 rows repairable (RAMs with internal repair feature)

●

Supports read/write accesses mapped to the SRAM memory from any master

●

32 KB block powered by separate supply for standby operation

●

Byte, halfword, word and doubleword addressable

●

ECC performs single bit correction, double bit detection

1.5.10

Boot assist module (BAM)

The BAM is a block of read-only memory that is programmed once by ST and is identical for

all SPC564A70 MCUs. The BAM program is executed every time the MCU is powered on or

reset in normal mode. The BAM supports different modes of booting. They are:

●

Booting from internal flash memory

●

Serial boot loading (boot code is downloaded into RAM via eSCI or the FlexCAN and

then executed)

The BAM also reads the reset configuration half word (RCHW) from internal flash memory

and configures the SPC564A70 hardware accordingly. The BAM provides the following

features:

●

Sets up MMU to cover all resources and mapping of all physical addresses to logical

addresses with minimum address translation

●

Sets up MMU to allow user boot code to execute as either Power Architecture

technology code (default) or as VLE code

●

Location and detection of user boot code

●

Automatic switch to serial boot mode if internal flash is blank or invalid

●

Supports user programmable 64-bit password protection for serial boot mode

●

Supports serial bootloading via FlexCAN bus and eSCI using standard protocol

●

Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing

●

Supports serial bootloading of either Power Architecture technology code (default) or

VLE code

●

Supports booting from calibration bus interface

●

Supports censorship protection for internal flash memory

●

Provides an option to enable the core watchdog timer

●

Provides an option to disable the system watchdog timer

1.5.11

Enhanced modular input/output system (eMIOS)

The eMIOS timer module provides the capability to generate or measure events in

hardware.

SPC564A70L7 Datasheet(PDF) 21 Page - STMicroelectronics

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