A8603KESTR-R datasheet(19/42 Pages) ALLEGRO

19 / 42 page

Multiple-Output Regulator for

Automotive LCD Displays

A8603

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

An inverting charge pump is used to generate the negative voltage

for VGL. A representative block diagram is shown in Figure 6.

VOUT

CP21

CP22

VGL

AGND

Target Voltage

From boost

output

OCP

To boost

controller

CVGL

500

Discharge

0 V

DAC

I2C Register

0x03

1.8 V

Enable

Linear Regulator

–1× Charge

Pump

External

Silicon Diode

External

Fly Cap

Switching Sequence:

• S1 and D1 = on: charging external cap

• S2 and D2 = on: dumping to VGL

(external)

Figure 6: Representative Block Diagram of the VGL Negative Charge Pump Mode

The frequency of the charge pumps is the same as the boost

switching frequency (or external SYNC frequency). When an

external SYNC signal is used, it is internally converted into a

clock signal with the same frequency, but at 50% duty cycle.

Recommended values of the external flying capacitor, CFLYx, on

the CPxx pins depends on the switching frequency as shown in the

following table; a voltage rating of 25 V is sufficient.

Table 14: Recommended Flying Capacitor Values

Switching Frequency (MHz)

CFLYx (µF)

0.1

0.22

0.35

0.47

The value of the flying capacitor can be calculates as follows:

1. The equivalent series resistance of the flying capacitor is:

ESRFLY2 = 1 / ( fSW × CFLY2 )

(2)

2. Assuming a flying capacitor ripple voltage of 100 mV, and a

maximum output current of 20 mA, the series resistance is:

RFLY2 ≤ 0.1 (V) / 0.02 (A) = 5 Ω

3. Therefore at an fSW of 2 MHz, the required capacitance,

CFLY2, is 0.1 μF.

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