PIC12CE673-04SLASHP datasheet(66/116 Pages) MICROCHIP

66 / 116 page

PIC12CE67X

DS40181B-page 66

Preliminary

BTFSS

Bit Test f, Skip if Set

Syntax:

[

label ] BTFSS f,b

Operands:

≤ f ≤ 127

≤ b < 7

Operation:

skip if (f<b>) = 1

Status Affected:

None

Encoding:

11bb

bfff

ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

Words:

Cycles:

1(2)

Example

HERE

FALSE

TRUE

BTFSS

GOTO

•

FLAG,1

PROCESS_CODE

Before Instruction

PC =

address

HERE

After Instruction

if FLAG<1> = 0,

PC =

address FALSE

if FLAG<1> = 1,

PC =

address TRUE

CALL

Call Subroutine

Syntax:

[

label ] CALL k

Operands:

≤ k ≤ 2047

Operation:

(PC)+ 1

→ TOS,

→ PC<10:0>,

(PCLATH<4:3>)

→ PC<12:11>

Status Affected:

None

Encoding:

0kkk

kkkk

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL

is a two cycle instruction.

Words:

Cycles:

Example

HERE

CALL

THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF

Clear f

Syntax:

[

label ] CLRF

Operands:

≤ f ≤ 127

Operation:

00h

→ (f)

→ Z

Status Affected:

Encoding:

0001

1fff

ffff

Description:

The contents of register 'f' are cleared

and the Z bit is set.

Words:

Cycles:

Example

CLRF

FLAG_REG

Before Instruction

FLAG_REG

0x5A

After Instruction

FLAG_REG

0x00

CLRW

Clear W

Syntax:

[

label ] CLRW

Operands:

None

Operation:

00h

→ (W)

→ Z

Status Affected:

Encoding:

0001

0000

0011

Description:

W register is cleared. Zero bit (Z) is

set.

Words:

Cycles:

Example

CLRW

Before Instruction

0x5A

After Instruction

0x00

PIC12CE673-04/P Datasheet(PDF) 66 Page - Microchip Technology

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