PIC12CE673-04SLASHP datasheet(17/116 Pages) MICROCHIP

17 / 116 page

Preliminary

DS40181B-page 17

PIC12CE67X

4.2.2.3

INTCON REGISTER

The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the

TMR0 register overﬂow, GPIO Port change and Exter-

nal GP2/INT Pin interrupts.

Note:

Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

FIGURE 4-5:

INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0

R/W-x

GIE

PEIE

T0IE

INTE

GPIE

T0IF

INTF

GPIF

= Readable bit

W = Writable bit

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7

bit0

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6:

PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5:

T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4:

INTE: INT External Interrupt Enable bit

1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin

0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin

bit 3:

GPIE: GPIO Interrupt on Change Enable bit

1 = Enables the GPIO Interrupt on Change

0 = Disables the GPIO Interrupt on Change

bit 2:

T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software)

0 = TMR0 register did not overﬂow

bit 1:

INTF: INT External Interrupt Flag bit

1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)

0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur

bit 0:

GPIF: GPIO Interrupt on Change Flag bit

1 = GP0, GP1, or GP3 pins changed state (must be cleared in software)

0 = Neither GP0, GP1, nor GP3 pins have changed state

PIC12CE673-04/P Datasheet(PDF) 17 Page - Microchip Technology

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