PIC12CE673-04SLASHP datasheet(73/116 Pages) MICROCHIP

73 / 116 page

Preliminary

DS40181B-page 73

PIC12CE67X

SWAPF

Swap Nibbles in f

Syntax:

[

label ] SWAPF f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(f<3:0>)

→ (dest<7:4>),

(f<7:4>)

→ (dest<3:0>)

Status Affected:

None

Encoding:

1110

dfff

ffff

Description:

The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Words:

Cycles:

Example

SWAPF

REG,

Before Instruction

REG1

0xA5

After Instruction

REG1

0xA5

0x5A

TRIS

Load TRIS Register

Syntax:

[

label ] TRIS

Operands:

≤ f ≤ 7

Operation:

(W)

→ TRIS register f;

Status Affected: None

Encoding:

0000

0110

0fff

Description:

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Words:

Cycles:

Example

To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

XORLW

Exclusive OR Literal with W

Syntax:

[

label ]

XORLW k

Operands:

≤ k ≤ 255

Operation:

(W) .XOR. k

→ (W)

Status Affected:

Encoding:

1010

kkkk

Description:

The contents of the W register are

XOR’ed with the eight bit literal 'k'.

The result is placed in the W regis-

ter.

Words:

Cycles:

Example:

XORLW

0xAF

Before Instruction

0xB5

After Instruction

0x1A

XORWF

Exclusive OR W with f

Syntax:

[

label ] XORWF

f,d

Operands:

≤ f ≤ 127

∈ [0,1]

Operation:

(W) .XOR. (f)

→ (dest)

Status Affected:

Encoding:

0110

dfff

ffff

Description:

Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words:

Cycles:

Example

XORWF

REG

Before Instruction

REG

0xAF

0xB5

After Instruction

REG

0x1A

0xB5

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