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BLUENRG-2 Datasheet(PDF) 137 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 137 Page - STMicroelectronics |
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137 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 137/190 Table 171: WDG - LR register description: address offset WDG_BASE_ADDR+0x00 Bit Field name Reset RW Description 31:0 LOAD 0xFFFFFFFF RW Watchdog load value. Value from which the counter is to decrement. When this register is written to, the count is immediately restarted from the new value. Table 172: WDG - VAL register description: address offset WDG_BASE_ADDR+0x04 Bit Field name Reset RW Description 31:0 WDTVAL 0xFFFFFFFF R Watchdog current value. When read, returns the current value of the decrementing watchdog counter. A write has no effect. Table 173: WDG - CR register description: address offset WDG_BASE_ADDR+0x08 Bit Field name Reset RW Description 0 INTEN 0x0 RW Watchdog interrupt enable. Enable the interrupt event: 0: watchdog interrupt is disabled. 1: watchdog interrupt is enabled. 1 RESEN 0x0 RW Watchdog Reset enable. Enable the watchdog Reset output: 0: watchdog Reset is disabled. 1: watchdog Reset is enabled. 31:2 RESERVED 0x0 R RESERVED Table 174: WDG - ICR register description: address offset WDG_BASE_ADDR+0x0C Bit Field name Reset RW Description 31:0 WDTICLR 0x0 RW Watchdog interrupt clear: Writing any value will clear the watchdog interrupt and reloads the counter from the LR register. A read returns zero. Table 175: WDG - RIS register description: address offset WDG_BASE_ADDR+0x10 Bit Field name Reset RW Description 0 RIS 0x0 R Watchdog raw interrupt status bit. Reflects the status of the interrupt status from the watchdog: 0: watchdog interrupt is not active. 1: watchdog interrupt is active. Read-only bit. A write has no effect. 31:1 RESERVED 0x0 R RESERVED |
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