BLUENRG-2 datasheet(140/190 Pages) STMICROELECTRONICS

140 / 190 page

Functional details

BlueNRG-2

140/190

DocID030675 Rev 2



Minutes on six bits. Valid values are 0 to 59 (60, 61, 62 and 63 are invalid values,

programming the RTC_CWDR with these values leads to unpredictable behavior.)



Hours on five bits. Valid values are 0 to 23 (24 to 31 are invalid values, programming

the RTC_CWDR with these values leads to unpredictable behavior.)



The day of the week on three bits. Valid values are 1 (Sunday) to 7 (Saturday) (0 is an

invalid value, programming the RTC_CWDR with this value leads to unpredictable

behavior.)



The day of the month on five bits. Valid values are 1 to 31 for January, March, May,

July, August, October and December, 1 to 30 for April, June, September, and

November, 1 to 29 for February on leap years, or 1 to 28 for February on non-leap

years. All other values are invalid values. Programming the RTC_CWDR with these

values leads to unpredictable behavior.)



The month on four bits. Valid values are 1 (January) to 12 (December). 0, 13, 14 and

15 are invalid values, programming the RTC_CWDR with these values leads to

unpredictable behavior.

The RTC_CWYR register holds:



The year, from 0 to 4096

The clock watch time and date can be changed by writing new settings in the

RTC_CWDLR and RTC_CWYLR load registers. The new setting is transferred to the clock

watch counters on the next CLK1HZ rising edge after the RTC_CWDLR register has been

written.

After each increment of the clock watch counters, the RTC_CWDR and RTC_CWYR

registers are compared to the clock watch match registers, RTC_CWDMR and

RTC_CWYMR.

If both pairs of registers match, the internal interrupt signal RTCWINTR is raised.

To ignore the corresponding bit-field of the RTC_CWDR register during the comparison,

program the month (CWMONTHM), day of the month (CWDAYMM) or day of the week

(CWDAYWM) bit-fields of the RTC_CWDMR register with zero values.

To ignore the RTC_CWYR register during the comparison, program the year bit-fields of

RTC_CWYMR register with zero values.

3.15.2.3

RTC interrupts

The RTC generates two internal interrupt signals:



RTCINTR: raised when the two clock watch counter registers (RTC_CWDR and

RTC_CWYR) match the two clock watch alarm registers (RTC_CWDMR and

RTC_CWYMR). Some bit-

fields can be ‘don’t care’ during the comparison if a zero

value is used for year, month, day of month and day of week. The software must clear

this interrupt by writing 1 in the bit RTCCWIC of RTC_ICR register.



RTTINTR: raised when the full 32-bit down-counter RTC_TDR reaches zero and is

only cleared by writing 1 in the bit RTTIC of the RTC_ICR register. The most

significant carry bit of the counter detects the counter reaches zero. The software

must clear this interrupt by writing 1 in the bit RTCTIC of the RTC_ICR register.

Each individual interrupt can be masked by writing 0b to its corresponding interrupt mask

set/clear bit in the RTC_IMSC register. Both the raw interrupt status (prior to masking) and

the final interrupt status (after masking) for each individual interrupt signal can be read from

the RTC_RIS and RTC_MIS status registers.

The RTC delivers also a single combined interrupt signal, RTUINTR. This interrupt line is

the logical OR of the both internal interrupt signals described above and is the signal

connected to the processor interrupt line.

BLUENRG-2 Datasheet(PDF) 140 Page - STMicroelectronics

BLUENRG-2 Datasheet(HTML) 140 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL