BLUENRG-2 datasheet(144/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

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DocID030675 Rev 2

Table 183: RTC - CWYR register description: address offset RTC_BASE_ADDR+0x0C

Bit

Field name

Reset

Description

13:0

CWYEAR

0x2000

RTC clockwatch year value. Clockwatch year, in BCD format

is from 0 to 3999.

31:14

RESERVED

0x0

RESERVED

Table 184: RTC - CWYMR register description: address offset RTC_BASE_ADDR+0x10

Bit

Field name

Reset

Description

13:0

CWYEARM

0x2000

RTC clockwatch year match value. Clockwatch year match

value is in BCD format from 0 to 3999.

31:14

RESERVED

0x0

RESERVED

Table 185: RTC - CWYLR register description: address offset RTC_BASE_ADDR+0x14

Bit

Field name

Reset

Description

13:0

CWYEARL

0x0

RTC clockwatch year load value. Clockwatch year load value

is in BCD format from 0 to 3999.

31:14

RESERVED

0x0

RESERVED

Table 186: RTC - CTCR register description: address offset RTC_BASE_ADDR+0x18

Bit

Field name

Reset

Description

14:0

CKDIV

0x7FFF

Clock divider factor. This value plus one represents the

integer part of the CLK32K clock divider used to produce the

reference 1 Hz clock.

0x000: CLK1HZ clock is similar to CLK32K for RTC timer

and stopped for RTC clockwatch.

0x0001: 2 CLK32K clock cycles per CLK1HZ clock cycle.

...

0x7FFF: 32768 CLK32K clock cycles per CLK1HZ clock

cycle (default value after PORn Reset).

...

0xFFFF: CLK32K clock cycles per CLK1HZ clock cycle.

Writing to this bit-field will be disregarded if CWEN = 1. A

read returns the value of the CKDIV bit-field.

RESERVED

0x0

RESERVED

25:16

CKDEL

0x0

Trim delete count. This value represents the number of

CLK32K clock pulses to delete every 1023 CLK32K clock

cycles to get a better reference 1 Hz clock for incrementing

the RTC counter.

0x000: No CLK32K clock cycle is deleted every 1023

CLK1HZ clock cycles (default value after PORn Reset).

0x001: 1 CLK32K clock cycle is deleted every 1023 CLK1HZ

clock cycles.

...

0x3FF: 1023 CLK32K clock cycles are deleted every 1023

CLK1HZ clock cycles.

Writing to this bit-field will be disregarded if CWEN = 1. A

read returns the value of the CKDEL bit-field.

BLUENRG-2 Datasheet(PDF) 144 Page - STMicroelectronics

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