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BLUENRG-2 Datasheet(PDF) 145 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 145 Page - STMicroelectronics |
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145 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 145/190 Bit Field name Reset RW Description 26 CWEN 0x0 RW Clockwatch enable bit. When set to 1, the clockwatch is enabled. Once it is enabled, any write to this register has no effect until a power-on Reset. A read returns the value of the CWEN bit value. 31:27 RESERVED 0x0 R RESERVED Table 187: RTC - IMSC register description: address offset RTC_BASE_ADDR+0x1C Bit Field name Reset RW Description 0 WIMSC 0x0 RW RTC clock watch interrupt enable bit: When set to 0, clears the interrupt mask (default after PORn Reset). The interrupt is disabled. When set to 1, the interrupt for RTC clockwatch interrupt is enabled. 1 TIMSC 0x0 RW RTC timer interrupt enable bit: When set to 0, sets the mask for RTC timer interrupt (default after PORn reset). The interrupt is disabled. When set to 1, clears this mask and enables the interrupt. 31:2 RESERVED 0x0 R RESERVED Table 188: RTC - RIS register description: address offset RTC_BASE_ADDR+0x20 Bit Field name Reset RW Description 0 WRIS 0x0 R RTC clock watch raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC clock watch interrupt. 1 TRIS 0x0 R RTC timer raw interrupt status bit. Gives the raw interrupt state (prior to masking) of the RTC timer interrupt. 31:2 RESERVED 0x0 R RESERVED Table 189: RTC - MIS register description: address offset RTC_BASE_ADDR+0x24. Bit Field name Reset RW Description 0 WMIS 0x0 R RTC clock watch interrupt status bit. Gives the masked interrupt status (after masking) of the RTC clock watch interrupt WINTR. 1 TMIS 0x0 R RTC timer interrupt status bit. Gives the masked interrupt status (after masking) of the RTC timer interrupt TINTR. 31:2 RESERVED 0x0 R RESERVED Table 190: RTC - ICR register description: address offset RTC_BASE_ADDR+0x28 Bit Field name Reset RW Description 0 WIC 0x0 W RTC clock watch interrupt clear register bit. Clears the RTC clock watch interrupt WINTR. 0: No effect. 1: Clears the interrupt. |
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