| Electronic Components Datasheet Search |
|
BLUENRG-2 Datasheet(PDF) 149 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
BLUENRG-2 Datasheet(HTML) 149 Page - STMicroelectronics |
|
149 / 190 page ![]() BlueNRG-2 Functional details DocID030675 Rev 2 149/190 3.17 PDM stream processor The BlueNRG-2 integrates a digital filter for processing PDM stream coming from a digital microphone and inputting into a GPIO pin. The BlueNRG-2 outputs a 0.8MHz or 1.6MHz signal into a GPIO pin for providing the digital microphone with a frequency clock. 3.18 System timer (SysTick) The BlueNRG-2 includes a system timer (SysTick) that can be polled by software or can be configured to generate an interrupt. SysTick interrupt has its own entry in the vector table and therefore can have its own handler. 3.19 Public key accelerator (PKA) The Public Key Accelerator is for the computation of cryptographic public key primitives through elliptic curve cryptography (ECC) using a predefined prime modulus and a predefined curve. 3.19.1 PKA functional description The PKA core is clocked by the system clock divided by two and the PKA memory is clocked by system clock. This peripheral is addressed through the AHB, so the access must be at 32-bit or a hard fault is generated on the Cortex M0. The PKA works on a 1 KB dedicated RAM block located in 0xC0000400. The main features of the PKA block are: elliptic curve Diffie-Hellman (ECDH) public-private key pair calculation accelerator based on the Montgomery method for fast modular multiplications built-in Montgomery domain inward and outward transformations AMBA AHB lite slave interface with a reduced command set single port internal memory available for the system when the BlueNRG-2 PKA is not using it. The PKA and the PKA RAM are clock gated by default after reset,. so the clock must be enabled in CKGEN_SOC before using PKA functionality. The input data, output data and data verification result have specific locations in the PKA RAM. Table 204: PKA RAM data location Parameter description PKA RAM offset address Size (words) INPUT: ECC K value of kP 0x6C EOS(1) INPUT: input point P, coordinate X 0x90 EOS INPUT: input point P, coordinate Y 0xB4 EOS OUTPUT: output point P, coordinate X 0x90 EOS OUTPUT: output point P, coordinate Y 0xB4 EOS OUTPUT: error value 0x00 1 Notes: (1)ECC Operand Size |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |