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BLUENRG-2 Datasheet(PDF) 148 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 148 Page - STMicroelectronics |
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148 / 190 page ![]() Functional details BlueNRG-2 148/190 DocID030675 Rev 2 3.16.3 RNG registers RNG peripheral base address (RNG_BASE_ADDR) 0xB0000000 Table 200: RNG registers Address offset Name RW Reset Description 0x00 CR RW 0x00000000 RNG configuration register. Refer to the detailed description below. 0x04 SR R 0x00000000 RNG status register. Refer to the detailed description below. 0x08 VAL R 0x00000000 RNG 16-bit random value. Refer to the detailed description below. Table 201: RNG – CR register description: address offset RNG_BASE_ADDR+0x00 Bit Field name Reset RW Description 1:0 RESERVED 0x0 RW RESERVED 2 DIS 0x0 RW Set the state of the random number generator. 0: RNG is enable. 1: RNG is disabled. The internal free-running oscillators are put in power-down mode and the RNG clock is stopped at the input of the block. 31:3 RESERVED 0x00000000 RW RESERVED Table 202: RNG – SR register description: address offset RNG_BASE_ADDR+0x04 Bit Field name Reset RW Description 0 RDY 0x0 R New random value ready. 0: The VAL register value is not yet valid. If performing a read access to VAL, the host will be put on hold until a random value is available. 1: The VAL register contains a valid random number. This bit remains at 0 when the RNG is disabled (RNGDIS bit = 1b in CR) 31:1 RESERVED 0x00000000 R RESERVED Table 203: RNG – VAL register description: address offset RNG_BASE_ADDR+0x08 Bit Field name Reset RW Description 15:0 RANDOM_VALUE 0x0000 R The 16-bit random value. 31:16 RESERVED 0x0000 R RESERVED |
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