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BLUENRG-2 Datasheet(PDF) 146 Page - STMicroelectronics

Part # BLUENRG-2
Description  Bluetooth® low energy wireless system-on-chip
PDF  190 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

BLUENRG-2 Datasheet(HTML) 146 Page - STMicroelectronics

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Functional details
BlueNRG-2
146/190
DocID030675 Rev 2
Bit
Field name
Reset
RW
Description
1
TIC
0x0
W
RTC timer interrupt clear register bit. Clears the RTC timer
interrupt TINTR.
0: No effect.
1: Clears the interrupt.
31:2
RESERVED
0x0
R
RESERVED
Table 191: RTC
– TDR register description: address offset RTC_BASE_ADDR+0x2C
Bit
Field name
Reset
RW
Description
31:0
TDR
0xFFFFFFFF
R
RTC time load value.
Table 192: RTC - TCR register description: address offset RTC_BASE_ADDR+0x30
Bit
Field name
Reset
RW
Description
0
OS
0x0
RW
RTC Timer one shot count.
0: Periodic mode (default). When reaching zero, the
RTC timer raises its interrupt and is reloaded from the
LD content.
1: One-shot mode. When reaching zero, the RTC timer
raise its interrupt and stops.
1
EN
0x0
RW
RTC Timer enable bit.
0: The RTC timer is stopped on the next CLK32K cycle.
1: The RTC timer is enabled on the next CLK32K cycle.
When the RTC timer is stopped, the content of the
counter is frozen. A read returns the value of the EN bit.
This bit set by hardware when the TLR register is written
to while the counter is stopped. When the device is
active, this bit is cleared by hardware when the counter
reaches zero in one-shot mode.
2
S
0x0
RW
RTC Timer self-start bit. When written to 1b, each write
in a load register or a pattern will set EN to 1b, so, start
the counter in the next CLK32K cycle.
3
RESERVED
0x0
R
RESERVED
10:4
SP
0x0
RW
RTC Timer Pattern size. Number of pattern bits crossed
by the pointer. It defines the useful pattern size.
11
CLK
0x0
RW
RTC Timer clock.
0: The RTC timer is clocked by CLK32K.
1: The RTC timer is clocked by the trimmed clock.
12
BYPASS_GATED
0x0
RW
Enable or disable the internal clock gating:
0: The internal clock gating is activated.
1: No clock gating, clock is always enabled.
31:13
RESERVED
0x0
R
RESERVED
Table 193: RTC
– TLR1 register description: address offset RTC_BASE_ADDR+0x34
Bit
Field name
Reset
RW
Description
31:0
TLR1
0x00000000
RW
RTC timer first load value.



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