ISL8270MEVAL1Z datasheet(4/56 Pages) RENESAS

4 / 56 page

ISL8270M

FN8635 Rev.4.00

Page 4 of 56

Aug 17, 2017

Pin Configuration

ISL8270M

(40 LD HDA)

TOP VIEW

VDRVOUT

VIN

SYNC

DDC

XTEMP+

VSEN -

XTEMP -

VSEN+

SGND

VOUT

SGND

VSWH

PGND

UVLO

PGND

PHASE

PGND

VDRVIN

Pin Descriptions

LABEL

TYPE

DESCRIPTION

DDC

I/O

Digital-DC™ bus. This dedicated bus provides the communication channel between devices for features such as

sequencing and fault spreading. The DDC pin on all Digital-DC devices should be connected together. A pull-up

resistor is required for this application.

2XTEMP+

Differential external temperature sensor positive input pin.

3XTEMP-

Differential external temperature sensor negative input pin.

6VSEN+

Differential Output voltage sense feedback. Connect to the positive output regulation point.

7VSEN-

Differential Output voltage sense feedback. Connect to the negative output regulation point.

8VDRVOUT

PWR

Output of internal LDO for powering the internal gate driver block. Place a 10µF ceramic capacitor at this pin. LDO

output is dedicated to powering the internal gate driver stage only. Do not use this LDO for any other purpose.

9, 12, 23,

31, 34

PGND

PWR

Power ground. Refer to the “PCB Layout Guidelines” on page 20 for the PGND pad connections and decoupling

capacitors placement.

VDRVIN

PWR

Input supply to internal LDO for powering internal gate driver block. An RC filter is required if the VIN supply is

shared. Refer to the “PCB Layout Guidelines” on page 20.

VIN

PWR

Main input supply. Refer to the “PCB Layout Guidelines” on page 20 for the decoupling capacitors placement from

VIN to PGND.

ISL8270MEVAL1Z Datasheet(PDF) 4 Page - Renesas Technology Corp

ISL8270MEVAL1Z Datasheet(HTML) 4 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL