ISL97635

FN6434 Rev.3.00

Page 19 of 28

Sep 26, 2017

PWM Brightness Control Register (0x00)

The Brightness control resolution has 256 steps of PWM duty cycle

adjustment. The bit assignment is shown in Figure 24. All of the bits

in this Brightness Control Register can be read or write. Step 0

corresponds to the minimum step where the current is less than

10µA. Steps 1 to 255 represent the linear steps between 0.39% and

100% duty cycle with approximately 0.39% duty cycle adjustment

per step.

• An SMBus Write Byte cycle to Register 0x00 sets the PWM

brightness level only if the backlight controller is in SMBus

mode (refer to Table 3 on page 19).

• An SMBus Read Byte cycle to Register 0x00 returns the

programmed PWM brightness level, regardless of the value of

PWM_SEL.

• An SMBus setting of 0xFF for Register 0x00 sets the backlight

controller to the maximum brightness.

• An SMBus setting of 0x00 for Register 0x00 sets the backlight

controller to the minimum brightness output in which the LED

current is guaranteed to be less than 10µA.

• Default value for Register 0x00 is 0xFF.

Device Control Register (0x01)

This register has 2 bits that control the operating mode of the

backlight controller and a single bit that controls the BL ON/OFF

state. The remaining bits are reserved. The bit assignment is

shown in Figure 25. All other bits in the Device Control Register

will read as low unless otherwise written. Bits 7 and 6 are not

implemented and will always read low.

The PWM_SEL bit determines whether the SMBus or PWMI input

should drive the output brightness in terms of PWM dimming.

When PWM_SEL bit is 1, the PWMI drives the output brightness

regardless of what the PWM_MD is.

When the PWM_SEL bit is 0, the PWM_MD bit selects the

manner in which the PWM dimming is to be interpreted; when

this bit is 1, the PWM dimming is based on the SMBus brightness

setting. When this bit is 0, the PWM dimming reflects a

percentage change in the current brightness programmed in the

SMBus Register 0x00, i.e. DPST (Display Power Saving

Technology) mode, as shown in Equation 15:

Where:

Cbt = Current brightness setting from SMBus Register 0x00 without

influence from the PWMI

PWMI = is the percent duty cycle of the PWMI

For example, the Cbt = 50% duty cycle programmed in the SMBus

Register 0x00 and the PWM frequency is tuned to be 200Hz with an

appropriate capacitor at the FPWM pin. On the other hand, PWMI is

fed with a 1kHz 30% high PWM signal. When PWM_SEL = 0 and

PWM_MD = 0, the device is in DPST operation where DPST

brightness = 15% PWM dimming at 200Hz.

• All reserved bits return a “0” when read.

• All reserved bits have no functional effect when written.

• All defined control bits return their current, latched value when

read.

• A value of 1 written to BL_CTL turns on the BL in 4ms or less after

the write cycle completes. The BL is deemed to be on when Bit 3

0x08

Configuration Register

VSC[1..0] = Short-circuit thresholds selection

FSW[2] = Switching frequencies selection

0x09

Output Channel Mask/Fault

Readout Register

CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In

Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled

TABLE 2B. DATA BIT DESCRIPTIONS (Continued)

ADDRESS

REGISTER

DATA BIT DESCRIPTIONS

VSC1

VSC0

OPERATION

0

X

No VSC error detection

1

0

VSC = 3.1V ±15%

1

1

VSC = 8V ±15%

OPERATION

TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL

REGISTER BITS 1 AND 2

PWM_MD

PWM_SEL

MODE

X1

PWMI Mode

10

SMBus Mode

0

0

SMBus and PWMI Mode with DPST

TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL

REGISTER BITS 1 AND 2

PWM_MD

PWM_SEL

MODE

DPST Brightness

Cbt PWMI



=

(EQ. 15)