12/19

¡ Semiconductor

MSM81C55-5RS/GS/JS

(2) Reading the C/S Register

The I/O and timer status can be accessed by reading the contents of the Status register

located at I/O address xxxxx000. The status word format is shown below:

(3) PA and PB Registers

These registers may be used as either input or output ports depending on the programmed

contents of the C/S register. They may also be used either in the basic mode or in the strobe

mode.

I/O address of the PA register: xxxxx001

I/O address of the PB register: xxxxx010

(4) PC Register

The PC register may be used as an input port, output port or control register depending on

the programmed contents of the C/S register. The I/O address of the PC register is

xxxxx011.

(5) Timer

The timer is a 14-bit down counter which counts TIMER IN pulses.

The low order byte of the timer register has an I/O address of xxxxx100, and the high order

byte of the register has an I/O address of xxxxx101.

The count length register (CLR) may be preset with two bytes of data. Bits 0 through 13 are

assigned to the count length and bits 14 and 15 specify the timer output mode. A read

operation of the CLR reads the contents of the counter and the pertinent output mode. The

initial value range which can initially be loaded into the counter is 2 through 3FFF hex. Bit

assignments to the timer counter and possible output modes are shown in the following.

INTR

A

Port A Interrupt Request

A

BF

Port A Buffer Full

INTE

A

INTR

B

B

BF

INTE

B

TIMER

Port A Interrupt Enable

Port B Interrupt Request

Port B Buffer Full

Port B Interrupt Enable

Timer Interrupt. This bit is set high when the timer

reaches TC, and is reset when the C/S register is read

or a hardware reset occurs.

Output Mode

High Order 6 Bits of Count Length

Low Order Byte of Count Length