SSD1306Z datasheet(20/65 Pages) ETC2

20 / 65 page

Solomon Systech

Apr 2008 P 20/59

Rev 1.1

SSD1306

8.1.5.1 I

2C-bus Write data

The I2C-bus interface gives access to write data and command into the device. Please refer to Figure 8-7 for

the write mode of I2C-bus in chronological order.

Figure 8-7 : I

2C-bus data format

8.1.5.2 Write mode for I

1) The master device initiates the data communication by a start condition. The definition of the start

condition is shown in Figure 8-8. The start condition is established by pulling the SDA from HIGH to

LOW while the SCL stays HIGH.

2) The slave address is following the start condition for recognition use. For the SSD1306, the slave

address is either “b0111100” or “b0111101” by changing the SA0 to LOW or HIGH (D/C pin acts as

SA0).

3) The write mode is established by setting the R/W# bit to logic “0”.

4) An acknowledgement signal will be generated after receiving one byte of data, including the slave

address and the R/W# bit. Please refer to the Figure 8-9 for the graphical representation of the

acknowledge signal. The acknowledge bit is defined as the SDA line is pulled down during the HIGH

period of the acknowledgement related clock pulse.

5) After the transmission of the slave address, either the control byte or the data byte may be sent across

the SDA. A control byte mainly consists of Co and D/C# bits following by six “0” ‘s.

a. If the Co bit is set as logic “0”, the transmission of the following information will contain

data bytes only.

b. The D/C# bit determines the next data byte is acted as a command or a data. If the D/C# bit is

set to logic “0”, it defines the following data byte as a command. If the D/C# bit is set to

logic “1”, it defines the following data byte as a data which will be stored at the GDDRAM.

The GDDRAM column address pointer will be increased by one automatically after each

data write.

6) Acknowledge bit will be generated after receiving each control byte or data byte.

7) The write mode will be finished when a stop condition is applied. The stop condition is also defined

in Figure 8-8. The stop condition is established by pulling the “SDA in” from LOW to HIGH while

the “SCL” stays HIGH.

01 111

Slave Address

m ≥ 0 words

n ≥ 0 bytes

MSB ……………….LSB

1 byte

Write mode

SSD1306

Slave Address

Control byte

Data byte

Control byte

Data byte

0 1 1 1 1 0

Control byte

Note:

Co – Continuation bit

D/C# – Data / Command Selection bit

ACK – Acknowledgement

SA0 – Slave address bit

R/W# – Read / Write Selection bit

S – Start Condition / P – Stop Condition

0 0 0 0 0 0

0 1 1 1 1 0

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