SSD1306Z datasheet(36/65 Pages) ETC2

36 / 65 page

Solomon Systech

Apr 2008 P 36/59

Rev 1.1

SSD1306

10.1.5 Set Page Address (22h)

This triple byte command specifies page start address and end address of the display data RAM. This

command also sets the page address pointer to page start address. This pointer is used to define the current

read/write page address in graphic display data RAM. If vertical address increment mode is enabled by

command 20h, after finishing read/write one page data, it is incremented automatically to the next page

address. Whenever the page address pointer finishes accessing the end page address, it is reset back to start

page address.

The figure below shows the way of column and page address pointer movement through the example: column

start address is set to 2 and column end address is set to 125, page start address is set to 1 and page end

address is set to 6; Horizontal address increment mode is enabled by command 20h. In this case, the graphic

display data RAM column accessible range is from column 2 to column 125 and from page 1 to page 6 only.

In addition, the column address pointer is set to 2 and page address pointer is set to 1. After finishing

read/write one pixel of data, the column address is increased automatically by 1 to access the next RAM

location for next read/write operation (solid line in Figure 10-5). Whenever the column address pointer

finishes accessing the end column 125, it is reset back to column 2 and page address is automatically

increased by 1 (solid line in Figure 10-5). While the end page 6 and end column 125 RAM location is

accessed, the page address is reset back to 1 and the column address is reset back to 2 (dotted line in Figure

10-5). .

Figure 10-5 : Example of Column and Row Address Pointer Movement

Col 0

Col 1

Col 2

…..

……. Col 125 Col 126 Col 127

PAGE0

PAGE1

PAGE6

PAGE7

10.1.6 Set Display Start Line (40h~7Fh)

This command sets the Display Start Line register to determine starting address of display RAM, by selecting

a value from 0 to 63. With value equal to 0, RAM row 0 is mapped to COM0. With value equal to 1, RAM

row 1 is mapped to COM0 and so on.

Refer to Table 10-1 for more illustrations.

10.1.7 Set Contrast Control for BANK0 (81h)

This command sets the Contrast Setting of the display. The chip has 256 contrast steps from 00h to FFh. The

segment output current increases as the contrast step value increases.

10.1.8

Set Segment Re-map (A0h/A1h)

This command changes the mapping between the display data column address and the segment driver. It

allows flexibility in OLED module design. Please refer to Table 9-1.

This command only affects subsequent data input. Data already stored in GDDRAM will have no changes.

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