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TDC-GPX2 Datasheet(PDF) 12 Page - ams AG |
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TDC-GPX2 Datasheet(HTML) 12 Page - ams AG |
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12 / 77 page ![]() Page 12 ams Datasheet Document Feedback [v1-03] 2017-Dec-18 TDC-GPX2 − Conver ter Characteristics Reference Clock and Stop Input Requirements General Conditions: VDD33 = 3.3V; VDD18 = 1.8V; TA = 0°C to 80°C; VID = 200mV; VIC = 1.25V; VIL = 0V; VIH = 3.3V Figure 11: Clock and Input Characteristics Symbol Description Condition TL Min Typ Max Unit fREFCLK Reference clock frequency High_Resolution = 0 (off ) High_Resolution = 1 (2x) High_Resolution = 2 (4x) III 2 2 2 5 5 5 12.5 12.5 10.0 MHz fREFOSC Reference oscillator frequency at pin 52,53 High_Resolution = 0 (off ) High_Resolution = 1 (2x) High_Resolution = 2 (4x) III 2 2 2 5 5 5 12.5 12.5 10.0 MHz TREFCLK Reference clock period III 83 200 500 ns Reference clock jitter V 100 ps Reference clock stability No requirement tPWH,STOP Minimum pulse width LVDS CMOS III 2 10 ns tPPS Minimum pulse-to-pulse spacing High_Resolution = 0 (off ) High_Resolution = 1 (2x) High_Resolution = 2 (4x) III 20 50 100 ns tPPS,CCH Minimum pulse-to-pulse spacing CHANNEL_COMBINE = 1 For a single pair of pulses. III 5 ns tSU,RST Setup time from RSTIDX to REFCLK III 5 ns tHD,RST Hold time from RSTIDX to REFCLK III 5 ns tSU,DIS Setup time from STOP to DISABLE III 5 ns tHD,DIS Hold Time from STOP to DISABLE III 5 ns tPIN_ENA Pin activation time from configuration of PIN_ENA… to valid data Pins: RSTIDX, DISABLE, REFCLK, STOP1…4 III 200 μs tPOR Delay between power-on or initialization reset and next communication Power-up, opcodes spiopc_ power & spiopc_init, pin III 100 μs |
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