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PCF2127T/2Y Datasheet(PDF) 29 Page - NXP Semiconductors |
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PCF2127T/2Y Datasheet(HTML) 29 Page - NXP Semiconductors |
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29 / 100 page  PCF2127 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 19 December 2014 29 of 100 NXP Semiconductors PCF2127 Accurate RTC with integrated quartz crystal for industrial applications After POR, the following mode is entered: • 32.768 kHz CLKOUT active • Power-On Reset Override (PORO) available to be set • 24-hour mode is selected • Battery switch-over is enabled • Battery low detection is enabled • Extra power fail detection is enabled The register values after power-on are shown in Table 5 on page 8. 8.8.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up the on-board test of the device. The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 18. All timings shown are required minimum. Fig 16. Dependency between POR and oscillator Fig 17. Power-On Reset (POR) system |
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