PCF2127TSLASH2Y datasheet(96/100 Pages) PHILIPS

96 / 100 page

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

96 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

26. Tables

Table 1.

Ordering information . . . . . . . . . . . . . . . . . . . . . .2

Table 2.

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3.

Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4.

Pin description of PCF2127 . . . . . . . . . . . . . . . .5

Table 5.

Table 6.

Control_1 - control and status register 1 (address

00h) bit allocation . . . . . . . . . . . . . . . . . . . . . .10

Table 7.

Control_1 - control and status register 1 (address

00h) bit description . . . . . . . . . . . . . . . . . . . . . .10

Table 8.

Control_2 - control and status register 2 (address

01h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 11

Table 9.

Control_2 - control and status register 2 (address

01h) bit description . . . . . . . . . . . . . . . . . . . . . 11

Table 10. Control_3 - control and status register 3 (address

02h) bit allocation . . . . . . . . . . . . . . . . . . . . . .12

Table 11. Control_3 - control and status register 3 (address

02h) bit description . . . . . . . . . . . . . . . . . . . . . .12

Table 12. CLKOUT_ctl - CLKOUT control register (address

0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .12

Table 13. CLKOUT_ctl - CLKOUT control register (address

0Fh) bit description . . . . . . . . . . . . . . . . . . . . . .12

Table 14. Temperature measurement period . . . . . . . . . .13

Table 15. CLKOUT frequency selection . . . . . . . . . . . . . .14

Table 16. Aging_offset - crystal aging offset register

(address 19h) bit allocation . . . . . . . . . . . . . . .14

Table 17. Aging_offset - crystal aging offset register

(address 19h) bit description . . . . . . . . . . . . . .14

Table 18. Frequency correction at 25 °C, typical . . . . . . .15

Table 19. RAM_addr_MSB - RAM address MSB register

(address 1Ah) bit allocation . . . . . . . . . . . . . . .16

Table 20. RAM_addr_MSB - RAM address MSB register

(address 1Ah) bit description . . . . . . . . . . . . . .16

Table 21. RAM_addr_LSB - RAM address LSB register

(address 1Bh) bit allocation . . . . . . . . . . . . . . .16

Table 22. RAM_addr_LSB - RAM address LSB register

(address 1Bh) bit description . . . . . . . . . . . . . .16

Table 23. RAM_wrt_cmd - RAM write command register

(address 1Ch) bit description . . . . . . . . . . . . . .16

Table 24. RAM_rd_cmd - RAM read command register

(address 1Dh) bit description . . . . . . . . . . . . . .16

Table 25. Power management control bit description . . .18

Table 26. Output pin BBS . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 27. Seconds - seconds and clock integrity register

(address 03h) bit allocation . . . . . . . . . . . . . . .30

Table 28. Seconds - seconds and clock integrity register

(address 03h) bit description . . . . . . . . . . . . . .30

Table 29. Seconds coded in BCD format . . . . . . . . . . . .31

Table 30. Minutes - minutes register (address 04h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 31. Minutes - minutes register (address 04h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 32. Hours - hours register (address 05h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 33. Hours - hours register (address 05h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 34. Days - days register (address 06h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 35. Days - days register (address 06h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 36. Weekdays - weekdays register (address 07h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 37. Weekdays - weekdays register (address 07h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 38. Weekday assignments . . . . . . . . . . . . . . . . . . 33

Table 39. Months - months register (address 08h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 40. Months - months register (address 08h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 41. Month assignments in BCD format . . . . . . . . . 34

Table 42. Years - years register (address 09h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 43. Years - years register (address 09h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 44. Second_alarm - second alarm register (address

0Ah) bit allocation . . . . . . . . . . . . . . . . . . . . . . 38

Table 45. Second_alarm - second alarm register (address

0Ah) bit description . . . . . . . . . . . . . . . . . . . . . 38

Table 46. Minute_alarm - minute alarm register (address

0Bh) bit allocation . . . . . . . . . . . . . . . . . . . . . . 38

Table 47. Minute_alarm - minute alarm register (address

0Bh) bit description . . . . . . . . . . . . . . . . . . . . . 38

Table 48. Hour_alarm - hour alarm register (address 0Ch)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 49. Hour_alarm - hour alarm register (address 0Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 50. Day_alarm - day alarm register (address 0Dh) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 51. Day_alarm - day alarm register (address 0Dh) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 52. Weekday_alarm - weekday alarm register

(address 0Eh) bit allocation . . . . . . . . . . . . . . 40

Table 53. Weekday_alarm - weekday alarm register

(address 0Eh) bit description . . . . . . . . . . . . . . 40

Table 54. Watchdg_tim_ctl - watchdog timer control register

(address 10h) bit allocation . . . . . . . . . . . . . . . 41

Table 55. Watchdg_tim_ctl - watchdog timer control register

(address 10h) bit description . . . . . . . . . . . . . . 41

Table 56. Watchdg_tim_val - watchdog timer value register

(address 11h) bit allocation . . . . . . . . . . . . . . . 42

Table 57. Watchdg_tim_val - watchdog timer value register

(address 11h) bit description . . . . . . . . . . . . . . 42

Table 58. Programmable watchdog timer . . . . . . . . . . . . 42

Table 59. Specification of tw(rst) . . . . . . . . . . . . . . . . . . . . 44

Table 60. First period delay for timer counter . . . . . . . . . 45

Table 61. Flag location in register Control_2 . . . . . . . . . . 46

Table 62. Example values in register Control_2 . . . . . . . 46

Table 63. Example to clear only CDTF (bit 3) . . . . . . . . . 46

Table 64. Example to clear only AF (bit 4) . . . . . . . . . . . . 46

Table 65. Example to clear only MSF (bit 7) . . . . . . . . . . 47

Table 66. Example to clear both CDTF and MSF . . . . . . 47

Table 67. Timestp_ctl - timestamp control register (address

12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 50

PCF2127T/2Y Datasheet(PDF) 96 Page - NXP Semiconductors

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