PCF2127TSLASH2Y datasheet(98/100 Pages) PHILIPS

98 / 100 page

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

98 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

27. Figures

Fig 1.

Block diagram of PCF2127 . . . . . . . . . . . . . . . . . .3

Fig 2.

Pin configuration for PCF2127AT (SO20) . . . . . . .4

Fig 3.

Pin configuration for PCF2127T (SO16) . . . . . . . .4

Fig 4.

Position of the stubs from the package assembly

process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 5.

Handling address registers . . . . . . . . . . . . . . . . . .6

Fig 6.

Battery switch-over behavior in standard mode with

bit BIE set logic 1 (enabled) . . . . . . . . . . . . . . . . .20

Fig 7.

Battery switch-over behavior in direct switching

mode with bit BIE set logic 1 (enabled) . . . . . . . .21

Fig 8.

Battery switch-over circuit, simplified block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 9.

Battery low detection behavior with bit BLIE set logic

1 (enabled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 10. Typical application of the extra power fail detection

function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 11. PFO signal behavior when battery switch-over is

enabled in standard mode and

Vth(uvp) >(VBAT,Vth(sw)bat) . . . . . . . . . . . . . . . . . . .25

Fig 12. PFO signal behavior when battery switch-over is

enabled in direct switching mode

and Vth(uvp) < VBAT . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 13. PFO signal behavior when battery switch-over is

disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 14. Typical driving capability of VBBS: (VBBS - VDD) with

respect to the output load current IBBS. . . . . . . . .27

Fig 15. Power failure event due to battery discharge: reset

occurs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 16. Dependency between POR and oscillator . . . . . .29

Fig 17. Power-On Reset (POR) system. . . . . . . . . . . . . .29

Fig 18. Power-On Reset Override (PORO) sequence, valid

for both I2C-bus and SPI-bus. . . . . . . . . . . . . . . .30

Fig 19. Data flow of the time function. . . . . . . . . . . . . . . .35

Fig 20. Access time for read/write operations . . . . . . . . .36

Fig 21. Alarm function block diagram. . . . . . . . . . . . . . . .37

Fig 22. Alarm flag timing diagram . . . . . . . . . . . . . . . . . .40

Fig 23. WD_CD[1:0] = 10: watchdog activates an interrupt

when timed out . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 24. WD_CD[1:0] = 11: watchdog activates a reset pulse

when timed out . . . . . . . . . . . . . . . . . . . . . . . . . .44

Fig 25. General countdown timer behavior . . . . . . . . . . .45

Fig 26. Timestamp detection with two push-buttons on the

TS pin (for example, for tamper detection) . . . . .48

Fig 27. Interrupt block diagram . . . . . . . . . . . . . . . . . . . .54

Fig 28. INT example for SI and MI when TI_TP is logic 156

Fig 29. INT example for SI and MI when TI_TP is logic 056

Fig 30. Example of shortening the INT pulse by clearing the

MSF flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 31. Example of shortening the INT pulse by clearing the

CDTF flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 32. AF timing diagram . . . . . . . . . . . . . . . . . . . . . . . .58

Fig 33. STOP bit functional diagram . . . . . . . . . . . . . . . .60

Fig 34. STOP bit release timing . . . . . . . . . . . . . . . . . . . .61

Fig 35. Interface selection . . . . . . . . . . . . . . . . . . . . . . . .62

Fig 36. SDI, SDO configurations . . . . . . . . . . . . . . . . . . .62

Fig 37. Data transfer overview . . . . . . . . . . . . . . . . . . . . .63

Fig 38. SPI-bus write examples . . . . . . . . . . . . . . . . . . . 64

Fig 39. SPI-bus read examples. . . . . . . . . . . . . . . . . . . . 65

Fig 40. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Fig 41. Definition of START and STOP conditions . . . . . 66

Fig 42. System configuration. . . . . . . . . . . . . . . . . . . . . . 67

Fig 43. Acknowledgement on the I2C-bus. . . . . . . . . . . . 67

Fig 44. Bus protocol, writing to registers . . . . . . . . . . . . . 68

Fig 45. Bus protocol, reading from registers . . . . . . . . . . 68

Fig 46. Bus protocol, writing to RAM . . . . . . . . . . . . . . . . 69

Fig 47. Bus protocol, reading from RAM . . . . . . . . . . . . . 70

Fig 48. Device diode protection diagram of PCF2127 . . 71

Fig 49. IOL on pin SDA/CE . . . . . . . . . . . . . . . . . . . . . . . 75

Fig 50. IDD as a function of temperature . . . . . . . . . . . . . 75

Fig 51. IDD as a function of VDD. . . . . . . . . . . . . . . . . . . . 76

Fig 52. Typical IDD as a function of the power management

settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Fig 53. Typical characteristic of frequency with respect to

temperature of PCF2127AT . . . . . . . . . . . . . . . . 79

Fig 54. Typical characteristic of frequency with respect to

temperature of PCF2127T . . . . . . . . . . . . . . . . . 79

Fig 55. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Fig 56. I2C-bus timing diagram; rise and fall times refer to

30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Fig 57. General application diagram . . . . . . . . . . . . . . . . 84

Fig 58. Package outline SOT163-1 (SO20)

of PCF2127AT. . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Fig 59. Package outline SOT162-1 (SO16)

of PCF2127T. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Fig 60. Footprint information for reflow soldering of

SOT163-1 (SO20) of PCF2127AT. . . . . . . . . . . . 87

Fig 61. Footprint information for reflow soldering of

SOT162-1 (SO16) of PCF2127T. . . . . . . . . . . . . 88

PCF2127T/2Y Datasheet(PDF) 98 Page - NXP Semiconductors

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