PCF2127TSLASH2Y datasheet(59/100 Pages) PHILIPS

59 / 100 page

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

59 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

8.14 External clock test mode

A test mode is available which allows on-board testing. In this mode, it is possible to set

up test conditions and control the operation of the RTC.

The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then

pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz)

with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided

down by a 26 divider chain called prescaler (see Table 84). The prescaler can be set into a

known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0.

STOP must be cleared before the prescaler can operate again.

From a stop condition, the first 1 second increment will take place after 32 positive edges

on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.

Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When

entering the test mode, no assumption as to the state of the prescaler can be made.

Operating example:

1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

2. Set bit STOP (register Control_1, STOP is logic 1).

3. Set time registers to desired value.

4. Clear STOP (register Control_1, STOP is logic 0).

5. Apply 32 clock pulses to CLKOUT.

6. Read time registers to see the first change.

7. Apply 64 clock pulses to CLKOUT.

8. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

8.15 STOP bit function

The function of the STOP bit is to allow for accurate starting of the time circuits. STOP

causes the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks

are generated. The time circuits can then be set and will not increment until the STOP bit

is released. STOP doesn't affect the CLKOUT signal but the output of the prescaler in the

range of 32 Hz to 1 Hz (see Figure 33).

PCF2127T/2Y Datasheet(PDF) 59 Page - NXP Semiconductors