PCF2127TSLASH2Y datasheet(58/100 Pages) PHILIPS

58 / 100 page

PCF2127

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 19 December 2014

58 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

8.13.4 Watchdog timer interrupts

The generation of interrupts from the watchdog timer is controlled using the WD_CD[1:0]

bits (register Watchdg_tim_ctl). The interrupt is generated as an active signal which

follows the status of the watchdog timer flag WDTF (register Control_2). No pulse

generation is possible for watchdog timer interrupts.

The interrupt is cleared when the flag WDTF is reset. WDTF is a read-only bit and cannot

be cleared by command. Instructions for clearing it can be found in Section 8.11.6.

8.13.5 Alarm interrupts

Generation of interrupts from the alarm function is controlled by the bit AIE (register

Control_2). If AIE is enabled, the INT pin follows the status of bit AF (register Control_2).

Clearing AF immediately clears INT. No pulse generation is possible for alarm interrupts.

8.13.6 Timestamp interrupts

Interrupt generation from the timestamp function is controlled using the TSIE bit (register

Control_2). If TSIE is enabled, the INT pin follows the status of the flags TSFx. Clearing

the flags TSFx immediately clears INT. No pulse generation is possible for timestamp

interrupts.

8.13.7 Battery switch-over interrupts

Generation of interrupts from the battery switch-over is controlled by the BIE bit (register

Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3

(see Table 81). Clearing BF immediately clears INT. No pulse generation is possible for

battery switch-over interrupts.

8.13.8 Battery low detection interrupts

Generation of interrupts from the battery low detection is controlled by the BLIE bit

(register Control_3). If BLIE is enabled, the INT pin follows the status of bit BLF (register

Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when

bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared by

command.

Example where only the minute alarm is used and no other interrupts are enabled.

Fig 32. AF timing diagram

PCF2127T/2Y Datasheet(PDF) 58 Page - NXP Semiconductors