PCF2127TSLASH2Y datasheet(55/100 Pages) PHILIPS

55 / 100 page

PCF2127

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Product data sheet

Rev. 8 — 19 December 2014

55 of 100

NXP Semiconductors

PCF2127

Accurate RTC with integrated quartz crystal for industrial applications

• watchdog timer

• alarm

• timestamp

• battery switch-over

• battery low detection

The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the

interrupts generated from the second/minute timer (flag MSF in register Control_2) and

the countdown timer (flag CDTF in register Control_2) are pulsed signals or a

permanently active signal. All the other interrupt sources generate a permanently active

interrupt signal which follows the status of the corresponding flags. When the interrupt

sources are all disabled, INT remains high-impedance.

• The flags MSF, CDTF, AF, TSFx, and BF can be cleared by command.

• The flag WDTF is read only. How it can be cleared is explained in Section 8.11.6.

• The flag BLF is read only. It is cleared automatically from the battery low detection

circuit when the battery is replaced.

8.13.1 Minute and second interrupts

Minute and second interrupts are generated by predefined timers. The timers can be

enabled independently from one another by the bits MI and SI in register Control_1.

However, a minute interrupt enabled on top of a second interrupt cannot be

distinguishable since it occurs at the same time.

The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or

the minutes counter increments according to the enabled interrupt (see Table 82). The

MSF flag can be cleared by command.

When MSF is set logic 1:

• If TI_TP is logic 1, the interrupt is generated as a pulsed signal.

• If TI_TP is logic 0, the interrupt is permanently active signal that remains until MSF is

cleared.

Table 82.

Effect of bits MI and SI on pin INT and bit MSF

Result on INT

Result on MSF

no interrupt generated

MSF never set

an interrupt once per minute

MSF set when minutes

counter increments

an interrupt once per second

MSF set when seconds

counter increments

an interrupt once per second

MSF set when seconds

counter increments

PCF2127T/2Y Datasheet(PDF) 55 Page - NXP Semiconductors

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