JS28F320J3A-150 datasheet(68/72 Pages) INTEL

68 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

Appendix C Design Considerations

C.1

Three-Line Output Control

The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,

CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:

a. Lowest possible memory power dissipation.

b. Complete assurance that data bus contention will not occur.

To use these control inputs efficiently, an address decoder should enable the device (see Table 13)

while OE# should be connected to all memory devices and the system’s READ# control line. This

assures that only selected memory devices have active outputs while de-selected memory devices

are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent

unintended writes during system power transitions. POWERGOOD should also toggle during

system reset.

C.2

STS and Block Erase, Program, and Lock-Bit Configuration

Polling

STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a

hardware method of detecting block erase, program, and lock-bit configuration completion. It is

recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions

low after block erase, program, or lock-bit configuration commands and returns to High Z when

the WSM has finished executing the internal algorithm. For alternate configurations of the STS

signal, see the Configuration command.

STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.

STS, in default mode, is also High Z when the device is in block erase suspend (with programming

inactive), program suspend, or in reset/power-down mode.

C.3

Input Signal Transitions—Reducing Overshoots and

Undershoots When Using Buffers or Transceivers

As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory

devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory

specifications. (See “DC Voltage Characteristics” on page 20.) Many buffer/transceiver vendors

now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.

Internal output-damping resistors diminish the nominal output drive currents, while still leaving

sufficient drive capability for most applications. These internal output-damping resistors help

reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-

drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When

considering a buffer/transceiver interface design to flash, devices with internal output-damping

resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For

additional information, please refer to AP-647, 5 Volt Intel StrataFlash® Memory Design Guide

(Order Number: 292205).

JS28F320J3A-150 Datasheet(PDF) 68 Page - Intel Corporation

JS28F320J3A-150 Datasheet(HTML) 68 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL