JS28F320J3A-150 datasheet(23/72 Pages) INTEL

23 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

R12

tFLQV/

tFHQV

BYTE# to Output Delay

1000

1,2

R13

tFLQZ

BYTE# to Output in High Z

1000

1,2,5

R14

tEHEL

CEx High to CEx Low

1,2,5

R15

tAPA

Page Address Access Time

5, 6

R16

tGLQV

OE# to Array Output Delay

NOTES:

CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is

defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).

1. See AC Input/Output Reference Waveforms for the maximum allowable input slew

rate.

2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that

enables the device (see Table 13) without impact on tELQV.

3. See Figure 15, “Transient Input/Output Reference Waveform for VCCQ = 2.7 V–3.6

V” on page 29 and Figure 16, “Transient Equivalent Testing Load Circuit” on

page 30 for testing characteristics.

4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to

Status Register reads, query reads, or device identifier reads.

5. Sampled, not 100% tested.

6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2

(tAVQV).

Figure 9. Single Word Asynchronous Read Waveform

Table 8.

Read Operations (Sheet 2 of 2)

Asynchronous

Specifications

(All units in ns unless

otherwise noted)

VCC = 2.7 V–3.6 V

(3)

VCCQ = 2.7 V–3.6 V

(3)

Notes

Speed

Bin

-110

-115

-120

-125

-150

Sym

Parameter

Density

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

R11

R12

R13

R10

R16

Address [A]

CEx [E]

OE# [G]

WE# [W]

Data [D/Q]

BYT E#[F]

RP# [P]

JS28F320J3A-150 Datasheet(PDF) 23 Page - Intel Corporation

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