JS28F320J3A-150 datasheet(34/72 Pages) INTEL

34 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

9.1.4

Standby

CE0, CE1, and CE2 can disable the device (see Table 13 on page 33) and place it in standby mode.

This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are

placed in a high-impedance state independent of OE#. If deselected during block erase, program, or

lock-bit configuration, the WSM continues functioning, and consuming active power until the

operation completes.

9.1.5

Reset/Power-Down

RP# at VIL initiates the reset/power-down mode.

In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and

turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is

required after return from reset mode until initial memory access outputs are valid. After this wake-

up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is

set to 0x80.

During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In

default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the

reset operation is complete. Memory contents being altered are no longer valid; the data may be

partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time

tPHWL is required after RP# goes to logic-high (VIH) before another command can be written.

As with any automated device, it is important to assert RP# during system reset. When the system

comes out of reset, it expects to read from the flash memory. Automated flash memories provide

status information when accessed during block erase, program, or lock-bit configuration modes. If

a CPU reset occurs with no flash memory reset, proper initialization may not occur because the

flash memory may be providing status information instead of array data. Intel StrataFlash

memory family devices allow proper initialization following a system reset through the use of the

RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system

CPU.

JS28F320J3A-150 Datasheet(PDF) 34 Page - Intel Corporation