JS28F320J3A-150 datasheet(58/72 Pages) INTEL

58 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

Table 31. Protection Register Information

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

(P+E)h

Number of Protection register fields in JEDEC ID space.

“00h,” indicates that 256 protection bytes are available

3F:

--01

(P+F)h

(P+10)h

(P+11)h

(P+12)h

Protection Field 1: Protection Description

This field describes user-available One Time Programmable

(OTP) Protection Register bytes. Some are pre-programmed

with device-unique serial numbers. Others are user-

programmable. Bits 0-15 point to the Protection Register lock

byte, the section’s first byte. The following bytes are factory

pre-programmed and user-programmable.

bits 0-7 = Lock/bytes JEDEC-plane physical low address

bits 8-15 = Lock/bytes JEDEC-plane physical high address

bits 16-23 = “n” such that 2

n = factory pre-programmed bytes

bits 24-31 = “n” such that 2

n = user-programmable bytes

40:

41:

42:

43:

--80

--00

--03

80h

00h

8bytes

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

Table 32. Burst Read Information

Offset

(1)

P = 31h

Length

Description

(Optional Flash Features and Commands)

Add.

Hex

Code

Value

(P+13)h

Page Mode Read capability

bits 0–7 = “n” such that 2n HEX value represents the number

of read-page bytes. See offset 28h for device word width to

determine page-mode data output width. 00h indicates no

read page buffer.

44:

--03

8 byte

(P+14)h

Number of synchronous mode read configuration fields that

follow. 00h indicates no burst capability.

45:

--00

(P+15)h

Reserved for future use

46:

NOTE:

1. The variable P is a pointer which is defined at CFI offset 15h.

JS28F320J3A-150 Datasheet(PDF) 58 Page - Intel Corporation

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