TLE4943C datasheet(9/48 Pages) INFINEON

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TLE4943C

Data Sheet

V 1.2, July 2018

2.4

Block Diagram

Figure 4

Block Diagram

2.5

Functional Block Description

TLE4943C is composed of the following main blocks:

•

Hall elements (B1, B2, B3)

•

Analog to Digital Converter in the speed signal path (ADC)

•

Offset Digital to Analog Converter (Offset DAC)

•

Low Pass Filter (LPF)

•

Three Current modulator

•

Main Comparator (Main)

•

Analog to Digital Converter in the direction path (Direction ADC)

•

Digital Core (D-core)

•

Amplifier for speed and direction path

•

Current modulator

The speed signal dB, calculated out of B2-B1, is amplified and low pass filtered. Afterwards signal is digitized.

Algorithms in the D-Core for peak detection and offset calculation are executed. The offset is calculated out of two

detected extrema (max+min)/2. This offset is fed back into speed signal path with an Digital to Analog converter

to correct any offsets. The main comparator compares the speed signal with zero value. During uncalibrated

mode, output of speed pulse is triggered in the D-Core by exceeding a certain threshold (2 x dBlimit).

The direction signal is calculated out of all three Hall elements (described in Figure 4). The direction signal is

amplified, filtered and digitized. In the D-Core the direction is determined and the data protocol is issued and

converted into a current modulated signal. The protocol consists of the speed pulse, issued by zero crossing, and

other data bits determined by the D-Core.

Tracking

ADC

Tracking-ADC

Algorithm

LPF

Main

Offset-

DAC

D-Core

Peak Detection

and

Offset Calculation

Direction

ADC

LPF

Direction

Detection

AK Protocol:

-Peak value

- timing

3 current

modulator

B2 (right)

B3 (center)

B1 (left)

Speed Signal dB = B2 – B1

Direction Signal dBdir= B3 –( B1+B2 )/2

speed signal path

direction signal path

dBdir

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