FXLS8964AF datasheet(17/98 Pages) NXP

17 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

17 / 98

I2C Standard-

mode[1]

I2C Fast-mode[1]

I2C Fast-mode Plus[2]

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

SDA valid acknowledge

time[5]

tVD;ACK

—

3.45[4]

—

0.9[4]

—

0.45[4]

µs

SDA setup time

tSU;DAT

250

—

100[6]

—

SCL clock low time

tLOW

4.7

—

1.3

—

0.50

—

µs

SCL clock high time

tHIGH

4.0

—

0.6

—

0.26

—

µs

SDA and SCL rise time

—

1000

300

—

120

SDA and SCL fall

time[7][8]

—

300

20*(VDD/5.5)

300

20*(VDD/5.5)[2]

120

Pulse width of spikes on

SDA and SCL that are

suppressed by the input

filter

tSP

[1]

All values referred to VIH(min) and VIL(max) levels.

[2]

Needed to be backwards compatible with Fast mode.

[3]

tVD;DAT referred to the time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[4]

The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode respectively, but must be less than the maximum of tVD;DAT or

tVD;ACK by a transition time.

[5]

tVD;ACK = time for ACK signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

[6]

A Fast-mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. Also the acknowledge timing

must meet this set-up time.

[7]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This

allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum

specified tf.

[8]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when

considering bus timing.

SDA

SCL

tSU:STA

tHD:STA

tSP

tSU:STO

tVD:ACK

70%

30%

9th clock

tBUF

Figure 10. I2C slave timing diagram for Standard-mode, Fast-mode and Fast-mode Plus

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