FXLS8964AF datasheet(26/98 Pages) NXP

26 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

26 / 98

12 Operating modes

Table 14. FXLS8964AF operating modes descriptions

Mode

I2C/SPI

bus state

VDD

Description

OFF

Unavailable

< 1.71 V

Communication with FXLS8964AF is not possible, but

communications with other devices on the same I2C/SPI bus is

possible provided the VDD supply pin is left floating/unconnected and

not connected to GND.

If VDD is not left floating/unconnected, the ESD protection diodes on

the interface pins could become forward biased and clamp the bus,

preventing normal operation.

As soon as the supply reaches 1.71 V, the device BOOT process

begins.

BOOT

Unavailable

≥ 1.71 V

BT_MODE = GND:

In this phase, the device is initialized and any default configuration

parameters are loaded from OTP memory. When this phase is

complete, the SRC_BOOT bit is set and a TPULSE-BOOT1 µs pulse may

be signaled on either one of the INT1/2 pins (defaults to enabled on

the INT1 pin after POR).

BT_MODE = VDD:

In this phase, the device is initialized and any default configuration

parameters are loaded from OTP memory, along with any default

Motion Detection function specific parameters. When the default

configuration parameters are loaded from OTP memory, the

SRC_BOOT bit is set and a boot pulse, TPULSE-BOOT2, can be signaled

on the INT2 pin. By default, the boot pulse is routed to INT2 pin and

cannot be routed to INT1 pin.

Hibernate

Unavailable

≥ 1.71 V

The Wake-Up detection circuit is active, but all other analog and

digital blocks are disabled to minimize the current drawn on the VDD

pin. I2C and SPI interfaces are not available, and all previously written

BT_MODE = GND:

The host must toggle the SPI_CS_B / WAKE-UP pin (low-to-high or

high-to-low) in order to initiate a transition back into Standby mode

before attempting communications with the device. The host must wait

TBOOT1 ms for the boot process to complete.

BT_MODE = VDD:

The INT1/MOT_DET pin is set high (level sensitive) through an

external pull-up resistor; the device then exits Hibernate mode and

starts the BOOT process. The host must wait TBOOT2 ms for the

boot process to complete and the motion detection process to begin.

Communication with the device over the I2C or SPI interfaces is

possible after the BOOT process completes.

Standby

Available

≥ 1.71V

Sensor and analog blocks are disabled;

I2C and SPI interfaces are available.

FXLS8964AF Datasheet(PDF) 26 Page - NXP Semiconductors

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