STM32H723VG datasheet(50/227 Pages) STMICROELECTRONICS

50 / 227 page

Functional overview

STM32H723xE/G

50/227

DS13313 Rev 2

3.43

Universal serial bus on-the-go high-speed (OTG_HS)

The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral

that supports both full-speed and high-speed operations. It integrates the transceivers for

full-speed operation (12 Mbit/s) and a UTMI low-pin interface (ULPI) for high-speed

operation (480 Mbit/s). When using the USB OTG_HS interface in HS mode, an external

PHY device connected to the ULPI is required.

The USB OTG_HS peripheral is compliant with the USB 2.0 specification and with the OTG

2.0 specification. It features software-configurable endpoint setting and supports

suspend/resume. The USB OTG_HS controller requires a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

The main features are:

•

Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing

•

Supports the session request protocol (SRP) and host negotiation protocol (HNP)

•

8 bidirectional endpoints

•

16 host channels with periodic OUT support

•

Software configurable to OTG1.3 and OTG2.0 modes of operation

•

USB 2.0 LPM (Link Power Management) support

•

Battery Charging Specification Revision 1.2 support

•

Internal FS OTG PHY support

•

External HS or HS OTG operation supporting ULPI in SDR mode The OTG PHY is

connected to the microcontroller ULPI port through 12 signals. It can be clocked using

the 60 MHz output.

•

Internal USB DMA

•

HNP/SNP/IP inside (no need for any external resistor)

•

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

3.44

Ethernet MAC interface with dedicated DMA controller (ETH)

The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for

ethernet LAN communications through an industry-standard medium-independent interface

(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an

external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,

fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals

for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.

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